Line Coverage for Module :
tlul_err
| Line No. | Total | Covered | Percent |
TOTAL | | 26 | 26 | 100.00 |
CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
CONT_ASSIGN | 36 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 1 | 1 | 100.00 |
CONT_ASSIGN | 42 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
ALWAYS | 56 | 17 | 17 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
26 |
1 |
1 |
27 |
1 |
1 |
28 |
1 |
1 |
32 |
1 |
1 |
36 |
1 |
1 |
39 |
1 |
1 |
42 |
1 |
1 |
53 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
69 |
1 |
1 |
71 |
1 |
1 |
73 |
1 |
1 |
77 |
1 |
1 |
78 |
1 |
1 |
79 |
1 |
1 |
89 |
1 |
1 |
90 |
1 |
1 |
91 |
1 |
1 |
95 |
1 |
1 |
Cond Coverage for Module :
tlul_err
| Total | Covered | Percent |
Conditions | 35 | 35 | 100.00 |
Logical | 35 | 35 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 26
EXPRESSION (tl_i.a_opcode == PutFullData)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T5,T6 |
LINE 27
EXPRESSION (tl_i.a_opcode == PutPartialData)
----------------1----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 28
EXPRESSION (tl_i.a_opcode == Get)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 39
EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
--------------------1-------------------- ------2----- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T6,T11,T12 |
0 | 1 | 0 | Covered | T11,T12,T14 |
1 | 0 | 0 | Covered | T1,T2,T3 |
LINE 39
SUB-EXPRESSION (opcode_allowed & a_config_allowed)
-------1------ --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T49,T17,T47 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 42
EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
---------------1-------------- ----------------2---------------- -----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T49,T17,T47 |
0 | 0 | 1 | Covered | T1,T2,T3 |
0 | 1 | 0 | Covered | T1,T2,T3 |
1 | 0 | 0 | Covered | T3,T5,T6 |
LINE 42
SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T5,T6 |
LINE 42
SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
----------------1----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 42
SUB-EXPRESSION (tl_i.a_opcode == Get)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 71
EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
--------1--------
-1- | Status | Tests |
0 | Covered | T6,T7,T11 |
1 | Covered | T5,T7,T9 |
LINE 73
EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
--------1--------
-1- | Status | Tests |
0 | Covered | T6,T7,T11 |
1 | Covered | T5,T7,T9 |
LINE 95
EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
-----1----- ----2--- ------------------3-----------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T17,T32,T33 |
1 | 0 | 1 | Covered | T22,T49,T17 |
1 | 1 | 0 | Covered | T17,T47,T50 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 95
SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
---1-- -----2---- ------3-----
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T3,T5,T6 |
0 | 0 | 1 | Covered | T3,T5,T6 |
0 | 1 | 0 | Covered | T1,T2,T3 |
1 | 0 | 0 | Covered | T1,T2,T3 |
Branch Coverage for Module :
tlul_err
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
8 |
8 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if (tl_i.a_valid)
-2-: 61 case (tl_i.a_size)
-3-: 71 (tl_i.a_address[1]) ?
-4-: 73 (tl_i.a_address[1]) ?
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
'h0 |
- |
- |
Covered |
T1,T2,T5 |
1 |
'h1 |
1 |
- |
Covered |
T5,T7,T9 |
1 |
'h1 |
0 |
- |
Covered |
T6,T7,T11 |
1 |
'h1 |
- |
1 |
Covered |
T5,T7,T9 |
1 |
'h1 |
- |
0 |
Covered |
T6,T7,T11 |
1 |
'h00000002 |
- |
- |
Covered |
T1,T2,T3 |
1 |
default |
- |
- |
Covered |
T17,T32,T33 |
0 |
- |
- |
- |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
tlul_err
Assertion Details
dataWidthOnly32_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
149 |
149 |
0 |
0 |
T1 |
2 |
2 |
0 |
0 |
T2 |
2 |
2 |
0 |
0 |
T3 |
2 |
2 |
0 |
0 |
T4 |
2 |
2 |
0 |
0 |
T5 |
2 |
2 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_err
| Line No. | Total | Covered | Percent |
TOTAL | | 26 | 16 | 61.54 |
CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
CONT_ASSIGN | 36 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 1 | 1 | 100.00 |
CONT_ASSIGN | 42 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
ALWAYS | 56 | 17 | 7 | 41.18 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
26 |
1 |
1 |
27 |
1 |
1 |
28 |
1 |
1 |
32 |
1 |
1 |
36 |
1 |
1 |
39 |
1 |
1 |
42 |
1 |
1 |
53 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
60 |
1 |
1 |
61 |
0 |
1 |
63 |
0 |
1 |
64 |
0 |
1 |
65 |
0 |
1 |
69 |
0 |
1 |
71 |
0 |
1 |
73 |
0 |
1 |
77 |
0 |
1 |
78 |
0 |
1 |
79 |
0 |
1 |
89 |
1 |
1 |
90 |
1 |
1 |
91 |
1 |
1 |
95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_err
| Total | Covered | Percent |
Conditions | 35 | 20 | 57.14 |
Logical | 35 | 20 | 57.14 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 26
EXPRESSION (tl_i.a_opcode == PutFullData)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T5 |
LINE 27
EXPRESSION (tl_i.a_opcode == PutPartialData)
----------------1----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 28
EXPRESSION (tl_i.a_opcode == Get)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 39
EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
--------------------1-------------------- ------2----- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Not Covered | |
0 | 0 | 1 | Not Covered | |
0 | 1 | 0 | Not Covered | |
1 | 0 | 0 | Covered | T1,T2,T3 |
LINE 39
SUB-EXPRESSION (opcode_allowed & a_config_allowed)
-------1------ --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Not Covered | |
LINE 42
EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
---------------1-------------- ----------------2---------------- -----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Not Covered | |
0 | 0 | 1 | Covered | T1,T2,T3 |
0 | 1 | 0 | Covered | T1,T2,T3 |
1 | 0 | 0 | Covered | T3,T5 |
LINE 42
SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T5 |
LINE 42
SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
----------------1----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 42
SUB-EXPRESSION (tl_i.a_opcode == Get)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 71
EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
--------1--------
-1- | Status | Tests |
0 | Not Covered | |
1 | Not Covered | |
LINE 73
EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
--------1--------
-1- | Status | Tests |
0 | Not Covered | |
1 | Not Covered | |
LINE 95
EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
-----1----- ----2--- ------------------3-----------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 95
SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
---1-- -----2---- ------3-----
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T3,T5 |
0 | 0 | 1 | Not Covered | |
0 | 1 | 0 | Covered | T1,T2,T3 |
1 | 0 | 0 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_err
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
1 |
12.50 |
IF |
60 |
8 |
1 |
12.50 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if (tl_i.a_valid)
-2-: 61 case (tl_i.a_size)
-3-: 71 (tl_i.a_address[1]) ?
-4-: 73 (tl_i.a_address[1]) ?
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
'h0 |
- |
- |
Not Covered |
|
1 |
'h1 |
1 |
- |
Not Covered |
|
1 |
'h1 |
0 |
- |
Not Covered |
|
1 |
'h1 |
- |
1 |
Not Covered |
|
1 |
'h1 |
- |
0 |
Not Covered |
|
1 |
'h00000002 |
- |
- |
Not Covered |
|
1 |
default |
- |
- |
Not Covered |
|
0 |
- |
- |
- |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_err
Assertion Details
dataWidthOnly32_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
5 |
5 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_reg_if.u_err
| Line No. | Total | Covered | Percent |
TOTAL | | 26 | 26 | 100.00 |
CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
CONT_ASSIGN | 36 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 1 | 1 | 100.00 |
CONT_ASSIGN | 42 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
ALWAYS | 56 | 17 | 17 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
26 |
1 |
1 |
27 |
1 |
1 |
28 |
1 |
1 |
32 |
1 |
1 |
36 |
1 |
1 |
39 |
1 |
1 |
42 |
1 |
1 |
53 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
69 |
1 |
1 |
71 |
1 |
1 |
73 |
1 |
1 |
77 |
1 |
1 |
78 |
1 |
1 |
79 |
1 |
1 |
89 |
1 |
1 |
90 |
1 |
1 |
91 |
1 |
1 |
95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_reg_if.u_err
| Total | Covered | Percent |
Conditions | 35 | 35 | 100.00 |
Logical | 35 | 35 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 26
EXPRESSION (tl_i.a_opcode == PutFullData)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T5,T6 |
LINE 27
EXPRESSION (tl_i.a_opcode == PutPartialData)
----------------1----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 28
EXPRESSION (tl_i.a_opcode == Get)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 39
EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
--------------------1-------------------- ------2----- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T6,T11,T12 |
0 | 1 | 0 | Covered | T11,T12,T14 |
1 | 0 | 0 | Covered | T3,T6,T7 |
LINE 39
SUB-EXPRESSION (opcode_allowed & a_config_allowed)
-------1------ --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T49,T17,T47 |
1 | 0 | Covered | T3,T6,T7 |
1 | 1 | Covered | T1,T2,T3 |
LINE 42
EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
---------------1-------------- ----------------2---------------- -----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T49,T17,T47 |
0 | 0 | 1 | Covered | T1,T2,T3 |
0 | 1 | 0 | Covered | T1,T2,T3 |
1 | 0 | 0 | Covered | T3,T5,T6 |
LINE 42
SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T5,T6 |
LINE 42
SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
----------------1----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 42
SUB-EXPRESSION (tl_i.a_opcode == Get)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 71
EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
--------1--------
-1- | Status | Tests |
0 | Covered | T6,T7,T11 |
1 | Covered | T5,T7,T9 |
LINE 73
EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
--------1--------
-1- | Status | Tests |
0 | Covered | T6,T7,T11 |
1 | Covered | T5,T7,T9 |
LINE 95
EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
-----1----- ----2--- ------------------3-----------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T17,T32,T33 |
1 | 0 | 1 | Covered | T22,T49,T17 |
1 | 1 | 0 | Covered | T17,T47,T50 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 95
SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
---1-- -----2---- ------3-----
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T3,T6,T7 |
0 | 0 | 1 | Covered | T3,T5,T6 |
0 | 1 | 0 | Covered | T2,T3,T4 |
1 | 0 | 0 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_reg_if.u_err
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
8 |
8 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if (tl_i.a_valid)
-2-: 61 case (tl_i.a_size)
-3-: 71 (tl_i.a_address[1]) ?
-4-: 73 (tl_i.a_address[1]) ?
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
'h0 |
- |
- |
Covered |
T1,T2,T5 |
1 |
'h1 |
1 |
- |
Covered |
T5,T7,T9 |
1 |
'h1 |
0 |
- |
Covered |
T6,T7,T11 |
1 |
'h1 |
- |
1 |
Covered |
T5,T7,T9 |
1 |
'h1 |
- |
0 |
Covered |
T6,T7,T11 |
1 |
'h00000002 |
- |
- |
Covered |
T1,T2,T3 |
1 |
default |
- |
- |
Covered |
T17,T32,T33 |
0 |
- |
- |
- |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_reg_if.u_err
Assertion Details
dataWidthOnly32_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
144 |
144 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |