Unified Coverage Report :: Module

Module : prim_ram_1p_adv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.92	82.35	33.33			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_no_stubbed_memory.u_memory_1p	78.92	82.35	33.33			100.00	100.00

Module Instance : tb.dut.gen_no_stubbed_memory.u_memory_1p

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.92	82.35	33.33			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
47.29	62.50	33.33			60.00	33.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
73.90	83.72	36.90	93.90		55.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_mem	22.54	14.29				33.33	20.00

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_ram_1p_adv

	Line No.	Total	Covered	Percent
TOTAL		17	14	82.35
ALWAYS	106	3	3	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	117	1	0	0.00
CONT_ASSIGN	118	0	0
CONT_ASSIGN	210	0	0
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	213	1	0	0.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	241	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	245	0	0
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	266	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv' or '../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
106	1	1
107	1	1
109	1	1
113	1	1
114	1	1
115	1	1
116	1	1
117	0	1
118		unreachable
210		unreachable
211	1	1
213	0	1
217	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245		unreachable
263	1	1
264	0	1
266		unreachable

Cond Coverage for Module : prim_ram_1p_adv

	Total	Covered	Percent
Conditions	3	1	33.33
Logical	3	1	33.33
Non-Logical	0	0
Event	0	0

 LINE       109
 EXPRESSION (req_q & ((~write_q)))
             --1--   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

Branch Coverage for Module : prim_ram_1p_adv

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	106	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv' or '../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	106	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Module : prim_ram_1p_adv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CannotHaveEccAndParity_A	5	5	0	0

CannotHaveEccAndParity_A

Name	Attempts	Real Successes
Total	5	5
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1