Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	68	0	68	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	17	0	17	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	68	0	68	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	483	1		T1	2		T2	2		T3	3
all_values[1]	483	1		T1	2		T2	2		T3	3
all_values[2]	483	1		T1	2		T2	2		T3	3
all_values[3]	483	1		T1	2		T2	2		T3	3
all_values[4]	483	1		T1	2		T2	2		T3	3
all_values[5]	483	1		T1	2		T2	2		T3	3
all_values[6]	483	1		T1	2		T2	2		T3	3
all_values[7]	483	1		T1	2		T2	2		T3	3
all_values[8]	483	1		T1	2		T2	2		T3	3
all_values[9]	483	1		T1	2		T2	2		T3	3
all_values[10]	483	1		T1	2		T2	2		T3	3
all_values[11]	483	1		T1	2		T2	2		T3	3
all_values[12]	483	1		T1	2		T2	2		T3	3
all_values[13]	483	1		T1	2		T2	2		T3	3
all_values[14]	483	1		T1	2		T2	2		T3	3
all_values[15]	483	1		T1	2		T2	2		T3	3
all_values[16]	483	1		T1	2		T2	2		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5966	1		T1	32		T2	32		T3	48
auto[1]	2245	1		T1	2		T2	2		T3	3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4872	1		T1	34		T2	34		T3	51
auto[1]	3339	1		T35	123		T36	120		T24	119

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	68	0	68	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	54	1		T18	2		T21	2		T51	2
all_values[0]	auto[0]	auto[1]	102	1		T36	2		T24	5		T39	6
all_values[0]	auto[1]	auto[0]	231	1		T1	2		T2	2		T3	3
all_values[0]	auto[1]	auto[1]	96	1		T35	7		T36	5		T24	3
all_values[1]	auto[0]	auto[0]	266	1		T1	2		T2	2		T3	3
all_values[1]	auto[0]	auto[1]	115	1		T35	7		T36	1		T24	3
all_values[1]	auto[1]	auto[0]	21	1		T36	1		T92	1		T93	2
all_values[1]	auto[1]	auto[1]	81	1		T35	1		T36	5		T24	5
all_values[2]	auto[0]	auto[0]	261	1		T1	2		T2	2		T3	3
all_values[2]	auto[0]	auto[1]	101	1		T35	7		T36	5		T24	2
all_values[2]	auto[1]	auto[0]	27	1		T24	1		T39	2		T40	1
all_values[2]	auto[1]	auto[1]	94	1		T35	1		T36	3		T24	4
all_values[3]	auto[0]	auto[0]	257	1		T1	2		T2	2		T3	3
all_values[3]	auto[0]	auto[1]	101	1		T35	3		T36	2		T24	4
all_values[3]	auto[1]	auto[0]	20	1		T36	1		T24	1		T40	2
all_values[3]	auto[1]	auto[1]	105	1		T35	4		T36	4		T24	3
all_values[4]	auto[0]	auto[0]	262	1		T1	2		T2	2		T3	3
all_values[4]	auto[0]	auto[1]	90	1		T35	2		T36	8		T24	3
all_values[4]	auto[1]	auto[0]	14	1		T35	1		T93	1		T94	1
all_values[4]	auto[1]	auto[1]	117	1		T35	5		T24	5		T39	5
all_values[5]	auto[0]	auto[0]	269	1		T1	2		T2	2		T3	3
all_values[5]	auto[0]	auto[1]	88	1		T35	6		T36	1		T24	2
all_values[5]	auto[1]	auto[0]	31	1		T36	2		T24	1		T39	3
all_values[5]	auto[1]	auto[1]	95	1		T36	5		T24	5		T40	3
all_values[6]	auto[0]	auto[0]	265	1		T1	2		T2	2		T3	3
all_values[6]	auto[0]	auto[1]	124	1		T35	6		T36	2		T24	2
all_values[6]	auto[1]	auto[0]	18	1		T36	1		T95	1		T85	2
all_values[6]	auto[1]	auto[1]	76	1		T35	2		T36	4		T24	6
all_values[7]	auto[0]	auto[0]	268	1		T1	2		T2	2		T3	3
all_values[7]	auto[0]	auto[1]	82	1		T35	1		T36	3		T39	3
all_values[7]	auto[1]	auto[0]	19	1		T35	1		T24	3		T94	2
all_values[7]	auto[1]	auto[1]	114	1		T35	5		T36	5		T24	4
all_values[8]	auto[0]	auto[0]	270	1		T1	2		T2	2		T3	3
all_values[8]	auto[0]	auto[1]	95	1		T35	1		T36	4		T24	6
all_values[8]	auto[1]	auto[0]	30	1		T92	2		T93	1		T96	1
all_values[8]	auto[1]	auto[1]	88	1		T35	7		T36	3		T24	2
all_values[9]	auto[0]	auto[0]	265	1		T1	2		T2	2		T3	3
all_values[9]	auto[0]	auto[1]	127	1		T35	6		T36	7		T39	6
all_values[9]	auto[1]	auto[0]	16	1		T24	2		T39	1		T40	1
all_values[9]	auto[1]	auto[1]	75	1		T35	2		T36	1		T24	5
all_values[10]	auto[0]	auto[0]	283	1		T1	2		T2	2		T3	3
all_values[10]	auto[0]	auto[1]	84	1		T35	5		T36	2		T24	2
all_values[10]	auto[1]	auto[0]	19	1		T36	1		T40	3		T92	1
all_values[10]	auto[1]	auto[1]	97	1		T35	1		T36	4		T24	6
all_values[11]	auto[0]	auto[0]	262	1		T1	2		T2	2		T3	3
all_values[11]	auto[0]	auto[1]	96	1		T35	4		T36	6		T24	4
all_values[11]	auto[1]	auto[0]	24	1		T39	1		T40	2		T92	3
all_values[11]	auto[1]	auto[1]	101	1		T35	3		T36	2		T24	3
all_values[12]	auto[0]	auto[0]	263	1		T1	2		T2	2		T3	3
all_values[12]	auto[0]	auto[1]	92	1		T35	7		T36	2		T24	1
all_values[12]	auto[1]	auto[0]	19	1		T36	1		T39	1		T97	1
all_values[12]	auto[1]	auto[1]	109	1		T35	1		T36	5		T24	7
all_values[13]	auto[0]	auto[0]	260	1		T1	2		T2	2		T3	3
all_values[13]	auto[0]	auto[1]	91	1		T36	2		T24	1		T39	3
all_values[13]	auto[1]	auto[0]	29	1		T35	1		T36	1		T96	3
all_values[13]	auto[1]	auto[1]	103	1		T35	7		T36	4		T24	7
all_values[14]	auto[0]	auto[0]	261	1		T1	2		T2	2		T3	3
all_values[14]	auto[0]	auto[1]	91	1		T35	5		T36	3		T24	6
all_values[14]	auto[1]	auto[0]	16	1		T85	2		T94	4		T98	1
all_values[14]	auto[1]	auto[1]	115	1		T35	3		T36	5		T24	1
all_values[15]	auto[0]	auto[0]	254	1		T1	2		T2	2		T3	3
all_values[15]	auto[0]	auto[1]	94	1		T35	5		T36	3		T24	1
all_values[15]	auto[1]	auto[0]	15	1		T35	1		T39	1		T94	2
all_values[15]	auto[1]	auto[1]	120	1		T35	2		T36	5		T24	7
all_values[16]	auto[0]	auto[0]	277	1		T1	2		T2	2		T3	3
all_values[16]	auto[0]	auto[1]	96	1		T35	5		T36	4		T24	4
all_values[16]	auto[1]	auto[0]	26	1		T24	3		T39	1		T95	1
all_values[16]	auto[1]	auto[1]	84	1		T35	2		T36	3		T39	1