Total Module Definition Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.90	90.32	74.27	97.14	31.25	76.43	97.99

Total modules in report: 53

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NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_sync_reqack	30.56	72.22	0.00			50.00	0.00
prim_reg_cdc_arb	37.90	49.67	62.79			39.13	0.00
prim_reg_cdc_arb	19.57					39.13	0.00
prim_reg_cdc_arb ( parameter DataWidth=10,ResetVal=0,DstWrReq=1 )	45.79	66.00	25.58
prim_reg_cdc_arb ( parameter DataWidth=2,ResetVal=0,DstWrReq=0 )	66.67	33.33	100.00
usb_fs_nb_in_pe	46.43	55.66	34.29		0.00	42.22	100.00
tlul_adapter_sram	61.33	76.92	39.82			50.00	78.57
prim_generic_clock_mux2	64.81	100.00	44.44				50.00
usbdev_iomux	65.62	81.25				50.00
usbdev_linkstate	66.21	75.00	63.77		33.33	58.93	100.00
usb_fs_tx	74.54	82.07	70.69		41.18	78.79	100.00
usb_fs_nb_out_pe	76.58	84.68	71.77		50.00	76.47	100.00
usb_fs_nb_pe	77.78	100.00	33.33				100.00
prim_fifo_sync	78.92	95.45	49.13			71.11	100.00
prim_fifo_sync	100.00						100.00
prim_fifo_sync ( parameter Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )	100.00	100.00
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )	42.31		42.31
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )	86.36	86.36
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PTRV_W=3,gen_normal_fifo.PTR_WIDTH=4 )	80.77	100.00	61.54
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PTRV_W=3,gen_normal_fifo.PTR_WIDTH=4 + Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )	80.00					80.00
prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )	63.47	90.91	41.18			58.33
prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )	42.31		42.31
prim_fifo_sync ( parameter Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PTRV_W=3,gen_normal_fifo.PTR_WIDTH=4 )	77.78	100.00	58.33			75.00
prim_fifo_sync_cnt	79.17	83.33				75.00
prim_fifo_sync_cnt	75.00					75.00
prim_fifo_sync_cnt ( parameter Depth=1,Width=2,Secure=0 )	77.78	77.78
prim_fifo_sync_cnt ( parameter Depth=8,Width=4,Secure=0 )	88.89	88.89
prim_generic_ram_1p	79.37	71.43				66.67	100.00
usbdev	82.72	89.92	54.76	93.90		75.00	100.00
prim_ram_1p_adv	87.25	82.35	66.67			100.00	100.00
usbdev_usbif	87.27	96.83	73.68			78.57	100.00
prim_subreg_arb	88.89	66.67	100.00			100.00
prim_subreg_arb	100.00					100.00
prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 )	100.00		100.00
prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 + DW=7,SwAccess=0,Mubi=0 + DW=5,SwAccess=0,Mubi=0 )	100.00	100.00
prim_subreg_arb ( parameter DW=1,SwAccess=1,Mubi=0 )	0.00	0.00
prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 )	100.00	100.00	100.00
prim_subreg_arb ( parameter DW=5,SwAccess=0,Mubi=0 )	100.00		100.00
prim_subreg_arb ( parameter DW=7,SwAccess=0,Mubi=0 )	100.00		100.00
prim_reg_cdc	92.86	100.00	71.43			100.00	100.00
usb_fs_rx	93.07	98.92	87.05			93.26
usb_fs_tx_mux	93.33	100.00	80.00			100.00
prim_intr_hw	93.75	100.00	75.00			100.00	100.00
tlul_assert	95.24	100.00				85.71	100.00
tlul_rsp_intg_gen	95.83	91.67					100.00
tlul_rsp_intg_gen	100.00						100.00
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 )	83.33	83.33
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 )	100.00	100.00
tlul_socket_1n	97.67	98.21	97.73			94.74	100.00
tlul_adapter_reg	98.47	100.00	93.88			100.00	100.00
usbdev_reg_top	99.60	99.72	98.69			100.00	100.00
tlul_data_integ_dec	100.00	100.00
tlul_cmd_intg_chk	100.00	100.00					100.00
prim_alert_sender	100.00			100.00
tlul_fifo_sync	100.00		100.00			100.00
prim_edge_detector	100.00	100.00				100.00
prim_onehot_check	100.00			100.00
prim_subreg	100.00	100.00	100.00			100.00
prim_subreg	100.00	100.00				100.00
prim_subreg ( parameter DW=1,SwAccess=3,RESVAL=0,Mubi=0 + DW=1,SwAccess=0,RESVAL,Mubi=0 + DW=1,SwAccess=1,RESVAL=0,Mubi=0 )	100.00		100.00
prim_subreg ( parameter DW=5,SwAccess=0,RESVAL=0,Mubi=0 )	100.00		100.00
prim_subreg ( parameter DW=7,SwAccess=0,RESVAL=0,Mubi=0 )	100.00		100.00
prim_filter	100.00	100.00	100.00			100.00
prim_secded_inv_39_32_dec	100.00			100.00
prim_generic_buf	100.00	100.00
prim_pulse_sync	100.00	100.00	100.00			100.00	100.00
prim_subreg_ext	100.00	100.00
prim_secded_inv_39_32_enc	100.00	100.00
tlul_sram_byte	100.00	100.00
tlul_err	100.00	100.00	100.00			100.00	100.00
prim_secded_inv_64_57_enc	100.00	100.00
prim_secded_inv_64_57_dec	100.00			100.00
prim_generic_flop	100.00	100.00				100.00
usbdev_csr_assert_fpv	100.00						100.00
tlul_data_integ_enc
prim_reg_we_check
prim_clock_mux2
prim_buf
prim_flop
prim_flop_2sync
tb
prim_ram_1p