Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
84.14	94.26	82.58	97.14	31.25	92.22	95.05	96.47

Total tests in report: 231

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
61.37	61.37	80.11	80.11	57.60	57.60	80.66	80.66	31.25	31.25	71.28	71.28	88.25	88.25	20.45	20.45	/workspace/coverage/default/13.usbdev_pkt_received.2361156625
72.97	11.60	87.83	7.72	77.70	20.10	87.03	6.37	31.25	0.00	88.78	17.50	89.90	1.65	48.33	27.88	/workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2822778853
78.16	5.18	88.94	1.11	78.95	1.25	89.89	2.86	31.25	0.00	88.78	0.00	90.10	0.21	79.18	30.86	/workspace/coverage/cover_reg_top/8.usbdev_intr_test.1149780235
79.81	1.66	94.47	5.53	81.02	2.07	90.33	0.44	31.25	0.00	92.13	3.35	90.31	0.21	79.18	0.00	/workspace/coverage/default/41.usbdev_smoke.282554538
80.91	1.10	94.47	0.00	81.02	0.00	90.77	0.44	31.25	0.00	92.13	0.00	90.31	0.00	86.43	7.25	/workspace/coverage/cover_reg_top/17.usbdev_intr_test.1768692695
81.87	0.96	94.47	0.00	81.53	0.51	90.99	0.22	31.25	0.00	92.22	0.09	91.55	1.24	91.08	4.65	/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1585522797
82.78	0.91	94.47	0.00	81.58	0.05	96.70	5.71	31.25	0.00	92.22	0.00	91.75	0.21	91.45	0.37	/workspace/coverage/default/1.usbdev_sec_cm.995094285
83.26	0.49	94.47	0.00	81.68	0.10	96.70	0.00	31.25	0.00	92.22	0.00	95.05	3.30	91.45	0.00	/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3486121699
83.66	0.40	94.47	0.00	81.68	0.00	96.70	0.00	31.25	0.00	92.22	0.00	95.05	0.00	94.24	2.79	/workspace/coverage/cover_reg_top/28.usbdev_intr_test.3944443966
83.75	0.09	94.47	0.00	82.32	0.64	96.70	0.00	31.25	0.00	92.22	0.00	95.05	0.00	94.24	0.00	/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1180365977
83.83	0.08	94.47	0.00	82.32	0.00	96.70	0.00	31.25	0.00	92.22	0.00	95.05	0.00	94.80	0.56	/workspace/coverage/cover_reg_top/0.usbdev_intr_test.1657734521
83.91	0.08	94.47	0.00	82.32	0.00	96.70	0.00	31.25	0.00	92.22	0.00	95.05	0.00	95.35	0.56	/workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.3461889656
83.97	0.06	94.47	0.00	82.32	0.00	97.14	0.44	31.25	0.00	92.22	0.00	95.05	0.00	95.35	0.00	/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.4116057871
84.03	0.05	94.47	0.00	82.32	0.00	97.14	0.00	31.25	0.00	92.22	0.00	95.05	0.00	95.72	0.37	/workspace/coverage/cover_reg_top/26.usbdev_intr_test.1516711800
84.08	0.05	94.47	0.00	82.32	0.00	97.14	0.00	31.25	0.00	92.22	0.00	95.05	0.00	96.10	0.37	/workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1456132303
84.11	0.03	94.64	0.17	82.35	0.03	97.14	0.00	31.25	0.00	92.22	0.00	95.05	0.00	96.10	0.00	/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.4278897478
84.13	0.03	94.64	0.00	82.35	0.00	97.14	0.00	31.25	0.00	92.22	0.00	95.05	0.00	96.28	0.19	/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.4019085197
84.16	0.03	94.64	0.00	82.35	0.00	97.14	0.00	31.25	0.00	92.22	0.00	95.05	0.00	96.47	0.19	/workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.4112841337
84.18	0.02	94.64	0.00	82.47	0.13	97.14	0.00	31.25	0.00	92.22	0.00	95.05	0.00	96.47	0.00	/workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3258750425
84.19	0.01	94.64	0.00	82.53	0.05	97.14	0.00	31.25	0.00	92.22	0.00	95.05	0.00	96.47	0.00	/workspace/coverage/default/10.usbdev_pkt_received.3102752908
84.19	0.01	94.64	0.00	82.55	0.03	97.14	0.00	31.25	0.00	92.22	0.00	95.05	0.00	96.47	0.00	/workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.4057175595
84.19	0.01	94.64	0.00	82.58	0.03	97.14	0.00	31.25	0.00	92.22	0.00	95.05	0.00	96.47	0.00	/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1195525301

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2861469830
/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1051185029
/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1370136512
/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.58262703
/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.49031574
/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.501671854
/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2570095889
/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2948302619
/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2647446532
/workspace/coverage/cover_reg_top/1.usbdev_intr_test.3084853782
/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2251181713
/workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2353013528
/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2479860011
/workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3399580864
/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2881564808
/workspace/coverage/cover_reg_top/10.usbdev_intr_test.2628335547
/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3327886801
/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1992604903
/workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.4235660644
/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2186226808
/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3582959630
/workspace/coverage/cover_reg_top/11.usbdev_intr_test.4278949920
/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3831349877
/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.228992069
/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3350086314
/workspace/coverage/cover_reg_top/12.usbdev_intr_test.2258568663
/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.256278854
/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3213886372
/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3158960120
/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.920544979
/workspace/coverage/cover_reg_top/13.usbdev_intr_test.3556438902
/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1717568033
/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.647446978
/workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.4244034521
/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.504162401
/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.896042074
/workspace/coverage/cover_reg_top/14.usbdev_intr_test.1441508889
/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3846745396
/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2894992482
/workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.2355646508
/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1772619706
/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3565498293
/workspace/coverage/cover_reg_top/15.usbdev_intr_test.2414435370
/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.115360281
/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2803209581
/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1373713976
/workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2024157736
/workspace/coverage/cover_reg_top/16.usbdev_intr_test.989133339
/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.4206577281
/workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3569795480
/workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2196726984
/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2956665876
/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2181017813
/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3201027429
/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1867865364
/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2996377375
/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1845415222
/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.2754531145
/workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3179638304
/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.955401202
/workspace/coverage/cover_reg_top/19.usbdev_intr_test.193029036
/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1980543857
/workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2211027313
/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.981182300
/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.769737327
/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3463782374
/workspace/coverage/cover_reg_top/2.usbdev_intr_test.2759401612
/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.68826170
/workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2237573493
/workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.44290780
/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.3545822721
/workspace/coverage/cover_reg_top/22.usbdev_intr_test.689888153
/workspace/coverage/cover_reg_top/24.usbdev_intr_test.3183464359
/workspace/coverage/cover_reg_top/27.usbdev_intr_test.237789029
/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2270465289
/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3918916032
/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3735911673
/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.4194399376
/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2899667963
/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3105353334
/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2867175229
/workspace/coverage/cover_reg_top/30.usbdev_intr_test.1633869957
/workspace/coverage/cover_reg_top/32.usbdev_intr_test.2944497191
/workspace/coverage/cover_reg_top/33.usbdev_intr_test.2864557475
/workspace/coverage/cover_reg_top/34.usbdev_intr_test.3046596235
/workspace/coverage/cover_reg_top/37.usbdev_intr_test.2471780608
/workspace/coverage/cover_reg_top/39.usbdev_intr_test.1836988203
/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3859353383
/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.167236364
/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.782698147
/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1306833557
/workspace/coverage/cover_reg_top/4.usbdev_intr_test.587185919
/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1517731825
/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3668975446
/workspace/coverage/cover_reg_top/41.usbdev_intr_test.858101492
/workspace/coverage/cover_reg_top/42.usbdev_intr_test.2413537482
/workspace/coverage/cover_reg_top/45.usbdev_intr_test.2513972277
/workspace/coverage/cover_reg_top/46.usbdev_intr_test.3857710179
/workspace/coverage/cover_reg_top/47.usbdev_intr_test.3594097587
/workspace/coverage/cover_reg_top/48.usbdev_intr_test.339443408
/workspace/coverage/cover_reg_top/49.usbdev_intr_test.286256672
/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.292463257
/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3148703636
/workspace/coverage/cover_reg_top/5.usbdev_intr_test.1879206358
/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2191295492
/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3936039163
/workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.569424558
/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3001594880
/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3053602491
/workspace/coverage/cover_reg_top/6.usbdev_intr_test.2031682809
/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3866878503
/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3649319042
/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2105625593
/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3498210930
/workspace/coverage/cover_reg_top/7.usbdev_intr_test.3341228712
/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3050913136
/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.300720687
/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2656899517
/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2673881801
/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3402823747
/workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.4022355659
/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.557824744
/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.4132804562
/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2440091181
/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2994587918
/workspace/coverage/default/0.usbdev_pkt_received.443236104
/workspace/coverage/default/0.usbdev_smoke.3120157539
/workspace/coverage/default/1.usbdev_smoke.984876338
/workspace/coverage/default/10.usbdev_smoke.2174778978
/workspace/coverage/default/11.usbdev_pkt_received.3930742420
/workspace/coverage/default/11.usbdev_smoke.4235494287
/workspace/coverage/default/12.usbdev_smoke.2369162148
/workspace/coverage/default/13.usbdev_smoke.2928194425
/workspace/coverage/default/14.usbdev_smoke.1138356700
/workspace/coverage/default/15.usbdev_pkt_received.2447008353
/workspace/coverage/default/15.usbdev_smoke.58329900
/workspace/coverage/default/16.usbdev_pkt_received.3253510501
/workspace/coverage/default/16.usbdev_smoke.3775910323
/workspace/coverage/default/18.usbdev_pkt_received.400153544
/workspace/coverage/default/18.usbdev_smoke.1072444783
/workspace/coverage/default/19.usbdev_smoke.690503586
/workspace/coverage/default/2.usbdev_pkt_received.80068186
/workspace/coverage/default/2.usbdev_sec_cm.3030584017
/workspace/coverage/default/2.usbdev_smoke.225047387
/workspace/coverage/default/20.usbdev_pkt_received.2741935488
/workspace/coverage/default/20.usbdev_smoke.3488775771
/workspace/coverage/default/21.usbdev_pkt_received.3875270829
/workspace/coverage/default/21.usbdev_smoke.713527618
/workspace/coverage/default/22.usbdev_pkt_received.373496706
/workspace/coverage/default/22.usbdev_smoke.586142098
/workspace/coverage/default/23.usbdev_pkt_received.1946363048
/workspace/coverage/default/23.usbdev_smoke.656886495
/workspace/coverage/default/24.usbdev_pkt_received.3047253106
/workspace/coverage/default/24.usbdev_smoke.1155866777
/workspace/coverage/default/25.usbdev_pkt_received.818166685
/workspace/coverage/default/25.usbdev_smoke.2899415423
/workspace/coverage/default/26.usbdev_pkt_received.3787174184
/workspace/coverage/default/26.usbdev_smoke.1671169039
/workspace/coverage/default/28.usbdev_pkt_received.3908569154
/workspace/coverage/default/28.usbdev_smoke.3493564772
/workspace/coverage/default/29.usbdev_pkt_received.1422278968
/workspace/coverage/default/29.usbdev_smoke.3072224194
/workspace/coverage/default/3.usbdev_pkt_received.1723183186
/workspace/coverage/default/3.usbdev_sec_cm.1483108042
/workspace/coverage/default/3.usbdev_smoke.1151479982
/workspace/coverage/default/30.usbdev_pkt_received.2150482664
/workspace/coverage/default/30.usbdev_smoke.4070727819
/workspace/coverage/default/31.usbdev_pkt_received.1884483231
/workspace/coverage/default/31.usbdev_smoke.2092280755
/workspace/coverage/default/32.usbdev_pkt_received.1234668572
/workspace/coverage/default/32.usbdev_smoke.2837412185
/workspace/coverage/default/33.usbdev_pkt_received.3550176399
/workspace/coverage/default/33.usbdev_smoke.1288079620
/workspace/coverage/default/34.usbdev_smoke.2728403456
/workspace/coverage/default/35.usbdev_pkt_received.3983184260
/workspace/coverage/default/35.usbdev_smoke.2508633247
/workspace/coverage/default/36.usbdev_pkt_received.2957750765
/workspace/coverage/default/36.usbdev_smoke.2071729794
/workspace/coverage/default/37.usbdev_pkt_received.2340580182
/workspace/coverage/default/37.usbdev_smoke.909903860
/workspace/coverage/default/38.usbdev_pkt_received.2360063117
/workspace/coverage/default/38.usbdev_smoke.1879177841
/workspace/coverage/default/39.usbdev_pkt_received.2782378116
/workspace/coverage/default/39.usbdev_smoke.3056100850
/workspace/coverage/default/4.usbdev_smoke.3611094401
/workspace/coverage/default/40.usbdev_smoke.2828994637
/workspace/coverage/default/42.usbdev_pkt_received.2077070990
/workspace/coverage/default/42.usbdev_smoke.1067476750
/workspace/coverage/default/43.usbdev_pkt_received.329822106
/workspace/coverage/default/43.usbdev_smoke.3906791617
/workspace/coverage/default/44.usbdev_pkt_received.4260518058
/workspace/coverage/default/44.usbdev_smoke.927748158
/workspace/coverage/default/45.usbdev_pkt_received.1734891392
/workspace/coverage/default/45.usbdev_smoke.1508771471
/workspace/coverage/default/46.usbdev_smoke.2181947867
/workspace/coverage/default/47.usbdev_smoke.3826334518
/workspace/coverage/default/48.usbdev_pkt_received.2773548913
/workspace/coverage/default/48.usbdev_smoke.2385098628
/workspace/coverage/default/49.usbdev_pkt_received.3658470347
/workspace/coverage/default/49.usbdev_smoke.1769493355
/workspace/coverage/default/5.usbdev_pkt_received.1786668662
/workspace/coverage/default/5.usbdev_smoke.2672983379
/workspace/coverage/default/6.usbdev_smoke.1958521904
/workspace/coverage/default/7.usbdev_pkt_received.63817604
/workspace/coverage/default/7.usbdev_smoke.4082796611
/workspace/coverage/default/8.usbdev_pkt_received.1225649354
/workspace/coverage/default/8.usbdev_smoke.988433634
/workspace/coverage/default/9.usbdev_pkt_received.2395273663
/workspace/coverage/default/9.usbdev_smoke.2150121398

Total test records in report: 231

tests.html | tests1.html | tests2.html | tests3.html

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/36.usbdev_smoke.2071729794	Feb 04 12:50:10 PM PST 24	Feb 04 12:50:22 PM PST 24	8380454165 ps
T2	/workspace/coverage/default/7.usbdev_smoke.4082796611	Feb 04 12:49:55 PM PST 24	Feb 04 12:50:07 PM PST 24	8374543566 ps
T3	/workspace/coverage/default/9.usbdev_pkt_received.2395273663	Feb 04 12:49:57 PM PST 24	Feb 04 12:50:08 PM PST 24	8406230762 ps
T4	/workspace/coverage/default/3.usbdev_smoke.1151479982	Feb 04 12:49:55 PM PST 24	Feb 04 12:50:06 PM PST 24	8367448180 ps
T7	/workspace/coverage/default/2.usbdev_sec_cm.3030584017	Feb 04 12:49:59 PM PST 24	Feb 04 12:50:10 PM PST 24	96623112 ps
T8	/workspace/coverage/default/2.usbdev_smoke.225047387	Feb 04 12:49:51 PM PST 24	Feb 04 12:50:01 PM PST 24	8370840235 ps
T9	/workspace/coverage/default/44.usbdev_smoke.927748158	Feb 04 12:50:14 PM PST 24	Feb 04 12:50:26 PM PST 24	8364862695 ps
T10	/workspace/coverage/default/22.usbdev_smoke.586142098	Feb 04 12:49:56 PM PST 24	Feb 04 12:50:08 PM PST 24	8367499033 ps
T5	/workspace/coverage/default/39.usbdev_pkt_received.2782378116	Feb 04 12:50:08 PM PST 24	Feb 04 12:50:21 PM PST 24	8398421931 ps
T6	/workspace/coverage/default/13.usbdev_pkt_received.2361156625	Feb 04 12:49:58 PM PST 24	Feb 04 12:50:14 PM PST 24	8373677065 ps
T13	/workspace/coverage/default/41.usbdev_smoke.282554538	Feb 04 12:50:13 PM PST 24	Feb 04 12:50:26 PM PST 24	8367673348 ps
T41	/workspace/coverage/default/23.usbdev_smoke.656886495	Feb 04 12:49:58 PM PST 24	Feb 04 12:50:14 PM PST 24	8385412937 ps
T42	/workspace/coverage/default/47.usbdev_smoke.3826334518	Feb 04 12:50:10 PM PST 24	Feb 04 12:50:23 PM PST 24	8373858180 ps
T43	/workspace/coverage/default/14.usbdev_smoke.1138356700	Feb 04 12:49:59 PM PST 24	Feb 04 12:50:18 PM PST 24	8364971438 ps
T49	/workspace/coverage/default/36.usbdev_pkt_received.2957750765	Feb 04 12:50:02 PM PST 24	Feb 04 12:50:20 PM PST 24	8384161172 ps
T114	/workspace/coverage/default/43.usbdev_smoke.3906791617	Feb 04 12:50:16 PM PST 24	Feb 04 12:50:26 PM PST 24	8378077096 ps
T28	/workspace/coverage/default/3.usbdev_sec_cm.1483108042	Feb 04 12:49:42 PM PST 24	Feb 04 12:49:45 PM PST 24	110975821 ps
T116	/workspace/coverage/default/39.usbdev_smoke.3056100850	Feb 04 12:50:09 PM PST 24	Feb 04 12:50:21 PM PST 24	8380200792 ps
T118	/workspace/coverage/default/45.usbdev_pkt_received.1734891392	Feb 04 12:50:16 PM PST 24	Feb 04 12:50:26 PM PST 24	8406641041 ps
T143	/workspace/coverage/default/37.usbdev_smoke.909903860	Feb 04 12:50:10 PM PST 24	Feb 04 12:50:23 PM PST 24	8381629976 ps
T139	/workspace/coverage/default/18.usbdev_smoke.1072444783	Feb 04 12:49:57 PM PST 24	Feb 04 12:50:08 PM PST 24	8371359740 ps
T11	/workspace/coverage/default/48.usbdev_smoke.2385098628	Feb 04 12:50:16 PM PST 24	Feb 04 12:50:28 PM PST 24	8370285319 ps
T74	/workspace/coverage/default/29.usbdev_smoke.3072224194	Feb 04 12:49:59 PM PST 24	Feb 04 12:50:18 PM PST 24	8365860097 ps
T12	/workspace/coverage/default/29.usbdev_pkt_received.1422278968	Feb 04 12:49:55 PM PST 24	Feb 04 12:50:06 PM PST 24	8388150591 ps
T131	/workspace/coverage/default/49.usbdev_smoke.1769493355	Feb 04 12:50:12 PM PST 24	Feb 04 12:50:24 PM PST 24	8370270351 ps
T75	/workspace/coverage/default/28.usbdev_pkt_received.3908569154	Feb 04 12:49:58 PM PST 24	Feb 04 12:50:15 PM PST 24	8385661408 ps
T106	/workspace/coverage/default/22.usbdev_pkt_received.373496706	Feb 04 12:49:53 PM PST 24	Feb 04 12:50:03 PM PST 24	8481368351 ps
T117	/workspace/coverage/default/15.usbdev_smoke.58329900	Feb 04 12:49:55 PM PST 24	Feb 04 12:50:07 PM PST 24	8372052114 ps
T107	/workspace/coverage/default/0.usbdev_smoke.3120157539	Feb 04 12:49:41 PM PST 24	Feb 04 12:49:52 PM PST 24	8369385054 ps
T110	/workspace/coverage/default/20.usbdev_smoke.3488775771	Feb 04 12:49:48 PM PST 24	Feb 04 12:49:57 PM PST 24	8368593096 ps
T122	/workspace/coverage/default/33.usbdev_smoke.1288079620	Feb 04 12:50:04 PM PST 24	Feb 04 12:50:19 PM PST 24	8383168602 ps
T109	/workspace/coverage/default/37.usbdev_pkt_received.2340580182	Feb 04 12:50:09 PM PST 24	Feb 04 12:50:22 PM PST 24	8404919214 ps
T144	/workspace/coverage/default/24.usbdev_smoke.1155866777	Feb 04 12:49:55 PM PST 24	Feb 04 12:50:07 PM PST 24	8369084116 ps
T44	/workspace/coverage/default/48.usbdev_pkt_received.2773548913	Feb 04 12:50:12 PM PST 24	Feb 04 12:50:25 PM PST 24	8407273540 ps
T151	/workspace/coverage/default/20.usbdev_pkt_received.2741935488	Feb 04 12:49:53 PM PST 24	Feb 04 12:50:03 PM PST 24	8380485897 ps
T71	/workspace/coverage/default/5.usbdev_smoke.2672983379	Feb 04 12:49:38 PM PST 24	Feb 04 12:49:50 PM PST 24	8369154858 ps
T152	/workspace/coverage/default/7.usbdev_pkt_received.63817604	Feb 04 12:49:57 PM PST 24	Feb 04 12:50:08 PM PST 24	8378652633 ps
T121	/workspace/coverage/default/44.usbdev_pkt_received.4260518058	Feb 04 12:50:08 PM PST 24	Feb 04 12:50:21 PM PST 24	8380750782 ps
T148	/workspace/coverage/default/11.usbdev_smoke.4235494287	Feb 04 12:49:56 PM PST 24	Feb 04 12:50:07 PM PST 24	8377814722 ps
T146	/workspace/coverage/default/28.usbdev_smoke.3493564772	Feb 04 12:49:57 PM PST 24	Feb 04 12:50:08 PM PST 24	8366376067 ps
T29	/workspace/coverage/default/1.usbdev_sec_cm.995094285	Feb 04 12:49:50 PM PST 24	Feb 04 12:49:53 PM PST 24	211947713 ps
T77	/workspace/coverage/default/8.usbdev_smoke.988433634	Feb 04 12:49:59 PM PST 24	Feb 04 12:50:17 PM PST 24	8375401312 ps
T123	/workspace/coverage/default/45.usbdev_smoke.1508771471	Feb 04 12:50:13 PM PST 24	Feb 04 12:50:24 PM PST 24	8381212350 ps
T153	/workspace/coverage/default/8.usbdev_pkt_received.1225649354	Feb 04 12:50:00 PM PST 24	Feb 04 12:50:18 PM PST 24	8394904261 ps
T129	/workspace/coverage/default/6.usbdev_smoke.1958521904	Feb 04 12:50:00 PM PST 24	Feb 04 12:50:19 PM PST 24	8371806717 ps
T127	/workspace/coverage/default/40.usbdev_smoke.2828994637	Feb 04 12:50:04 PM PST 24	Feb 04 12:50:19 PM PST 24	8368849976 ps
T154	/workspace/coverage/default/31.usbdev_smoke.2092280755	Feb 04 12:49:59 PM PST 24	Feb 04 12:50:17 PM PST 24	8371683780 ps
T128	/workspace/coverage/default/23.usbdev_pkt_received.1946363048	Feb 04 12:49:59 PM PST 24	Feb 04 12:50:15 PM PST 24	8381609339 ps
T111	/workspace/coverage/default/5.usbdev_pkt_received.1786668662	Feb 04 12:49:39 PM PST 24	Feb 04 12:49:51 PM PST 24	8405213361 ps
T149	/workspace/coverage/default/21.usbdev_smoke.713527618	Feb 04 12:49:51 PM PST 24	Feb 04 12:50:01 PM PST 24	8372131736 ps
T76	/workspace/coverage/default/16.usbdev_pkt_received.3253510501	Feb 04 12:49:50 PM PST 24	Feb 04 12:50:00 PM PST 24	8391751255 ps
T130	/workspace/coverage/default/11.usbdev_pkt_received.3930742420	Feb 04 12:49:58 PM PST 24	Feb 04 12:50:13 PM PST 24	8426815367 ps
T141	/workspace/coverage/default/25.usbdev_smoke.2899415423	Feb 04 12:49:57 PM PST 24	Feb 04 12:50:08 PM PST 24	8366124383 ps
T137	/workspace/coverage/default/21.usbdev_pkt_received.3875270829	Feb 04 12:49:58 PM PST 24	Feb 04 12:50:12 PM PST 24	8420193756 ps
T134	/workspace/coverage/default/38.usbdev_smoke.1879177841	Feb 04 12:50:13 PM PST 24	Feb 04 12:50:27 PM PST 24	8368592184 ps
T108	/workspace/coverage/default/31.usbdev_pkt_received.1884483231	Feb 04 12:49:55 PM PST 24	Feb 04 12:50:08 PM PST 24	8390778735 ps
T125	/workspace/coverage/default/46.usbdev_smoke.2181947867	Feb 04 12:50:09 PM PST 24	Feb 04 12:50:22 PM PST 24	8366613876 ps
T142	/workspace/coverage/default/43.usbdev_pkt_received.329822106	Feb 04 12:50:09 PM PST 24	Feb 04 12:50:23 PM PST 24	8400208216 ps
T45	/workspace/coverage/default/10.usbdev_pkt_received.3102752908	Feb 04 12:49:57 PM PST 24	Feb 04 12:50:08 PM PST 24	8402981487 ps
T135	/workspace/coverage/default/19.usbdev_smoke.690503586	Feb 04 12:49:50 PM PST 24	Feb 04 12:49:58 PM PST 24	8368488549 ps
T155	/workspace/coverage/default/30.usbdev_pkt_received.2150482664	Feb 04 12:49:59 PM PST 24	Feb 04 12:50:17 PM PST 24	8400255775 ps
T46	/workspace/coverage/default/3.usbdev_pkt_received.1723183186	Feb 04 12:49:59 PM PST 24	Feb 04 12:50:16 PM PST 24	8447682966 ps
T156	/workspace/coverage/default/26.usbdev_pkt_received.3787174184	Feb 04 12:49:58 PM PST 24	Feb 04 12:50:15 PM PST 24	8386703184 ps
T112	/workspace/coverage/default/42.usbdev_pkt_received.2077070990	Feb 04 12:50:05 PM PST 24	Feb 04 12:50:21 PM PST 24	8367124498 ps
T115	/workspace/coverage/default/38.usbdev_pkt_received.2360063117	Feb 04 12:50:09 PM PST 24	Feb 04 12:50:21 PM PST 24	8381554451 ps
T138	/workspace/coverage/default/32.usbdev_pkt_received.1234668572	Feb 04 12:50:04 PM PST 24	Feb 04 12:50:19 PM PST 24	8415271410 ps
T113	/workspace/coverage/default/15.usbdev_pkt_received.2447008353	Feb 04 12:49:59 PM PST 24	Feb 04 12:50:18 PM PST 24	8409529876 ps
T145	/workspace/coverage/default/24.usbdev_pkt_received.3047253106	Feb 04 12:49:57 PM PST 24	Feb 04 12:50:08 PM PST 24	8401476123 ps
T157	/workspace/coverage/default/25.usbdev_pkt_received.818166685	Feb 04 12:49:56 PM PST 24	Feb 04 12:50:08 PM PST 24	8424815464 ps
T132	/workspace/coverage/default/2.usbdev_pkt_received.80068186	Feb 04 12:49:56 PM PST 24	Feb 04 12:50:07 PM PST 24	8393888864 ps
T124	/workspace/coverage/default/9.usbdev_smoke.2150121398	Feb 04 12:50:01 PM PST 24	Feb 04 12:50:19 PM PST 24	8370558519 ps
T158	/workspace/coverage/default/4.usbdev_smoke.3611094401	Feb 04 12:49:40 PM PST 24	Feb 04 12:49:50 PM PST 24	8377087097 ps
T159	/workspace/coverage/default/10.usbdev_smoke.2174778978	Feb 04 12:50:03 PM PST 24	Feb 04 12:50:21 PM PST 24	8397319981 ps
T160	/workspace/coverage/default/35.usbdev_smoke.2508633247	Feb 04 12:50:05 PM PST 24	Feb 04 12:50:20 PM PST 24	8379555532 ps
T136	/workspace/coverage/default/32.usbdev_smoke.2837412185	Feb 04 12:49:59 PM PST 24	Feb 04 12:50:17 PM PST 24	8375791112 ps
T133	/workspace/coverage/default/16.usbdev_smoke.3775910323	Feb 04 12:49:59 PM PST 24	Feb 04 12:50:16 PM PST 24	8370063633 ps
T72	/workspace/coverage/default/0.usbdev_pkt_received.443236104	Feb 04 12:49:51 PM PST 24	Feb 04 12:50:00 PM PST 24	8372884763 ps
T147	/workspace/coverage/default/1.usbdev_smoke.984876338	Feb 04 12:49:58 PM PST 24	Feb 04 12:50:14 PM PST 24	8376180353 ps
T126	/workspace/coverage/default/35.usbdev_pkt_received.3983184260	Feb 04 12:50:05 PM PST 24	Feb 04 12:50:21 PM PST 24	8403479536 ps
T161	/workspace/coverage/default/49.usbdev_pkt_received.3658470347	Feb 04 12:50:16 PM PST 24	Feb 04 12:50:27 PM PST 24	8402692076 ps
T162	/workspace/coverage/default/30.usbdev_smoke.4070727819	Feb 04 12:50:01 PM PST 24	Feb 04 12:50:21 PM PST 24	8377526658 ps
T120	/workspace/coverage/default/33.usbdev_pkt_received.3550176399	Feb 04 12:50:04 PM PST 24	Feb 04 12:50:20 PM PST 24	8366371500 ps
T163	/workspace/coverage/default/13.usbdev_smoke.2928194425	Feb 04 12:49:55 PM PST 24	Feb 04 12:50:07 PM PST 24	8372451887 ps
T119	/workspace/coverage/default/34.usbdev_smoke.2728403456	Feb 04 12:50:08 PM PST 24	Feb 04 12:50:21 PM PST 24	8369539127 ps
T150	/workspace/coverage/default/18.usbdev_pkt_received.400153544	Feb 04 12:50:00 PM PST 24	Feb 04 12:50:18 PM PST 24	8370847398 ps
T140	/workspace/coverage/default/12.usbdev_smoke.2369162148	Feb 04 12:49:56 PM PST 24	Feb 04 12:50:07 PM PST 24	8404528196 ps
T73	/workspace/coverage/default/42.usbdev_smoke.1067476750	Feb 04 12:50:09 PM PST 24	Feb 04 12:50:21 PM PST 24	8373809972 ps
T164	/workspace/coverage/default/26.usbdev_smoke.1671169039	Feb 04 12:49:53 PM PST 24	Feb 04 12:50:02 PM PST 24	8370640966 ps
T32	/workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.4057175595	Feb 04 12:48:10 PM PST 24	Feb 04 12:48:15 PM PST 24	302277222 ps
T27	/workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2822778853	Feb 04 12:48:30 PM PST 24	Feb 04 12:48:37 PM PST 24	144427851 ps
T37	/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3486121699	Feb 04 12:48:24 PM PST 24	Feb 04 12:48:26 PM PST 24	70865155 ps
T33	/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3148703636	Feb 04 12:48:11 PM PST 24	Feb 04 12:48:13 PM PST 24	121736183 ps
T14	/workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2237573493	Feb 04 12:48:22 PM PST 24	Feb 04 12:48:27 PM PST 24	97188332 ps
T47	/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.955401202	Feb 04 12:48:46 PM PST 24	Feb 04 12:48:49 PM PST 24	143727489 ps
T15	/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2899667963	Feb 04 12:48:19 PM PST 24	Feb 04 12:48:23 PM PST 24	86206873 ps
T16	/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.557824744	Feb 04 12:48:18 PM PST 24	Feb 04 12:48:21 PM PST 24	35365594 ps
T35	/workspace/coverage/cover_reg_top/16.usbdev_intr_test.989133339	Feb 04 12:48:43 PM PST 24	Feb 04 12:48:48 PM PST 24	41273610 ps
T36	/workspace/coverage/cover_reg_top/17.usbdev_intr_test.1768692695	Feb 04 12:48:53 PM PST 24	Feb 04 12:48:57 PM PST 24	27672127 ps
T34	/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.4132804562	Feb 04 12:48:20 PM PST 24	Feb 04 12:48:23 PM PST 24	58997588 ps
T17	/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3158960120	Feb 04 12:48:24 PM PST 24	Feb 04 12:48:27 PM PST 24	46317780 ps
T18	/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3936039163	Feb 04 12:48:16 PM PST 24	Feb 04 12:48:20 PM PST 24	165323589 ps
T24	/workspace/coverage/cover_reg_top/8.usbdev_intr_test.1149780235	Feb 04 12:48:26 PM PST 24	Feb 04 12:48:28 PM PST 24	33074284 ps
T19	/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.4019085197	Feb 04 12:48:30 PM PST 24	Feb 04 12:48:36 PM PST 24	117117272 ps
T25	/workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3399580864	Feb 04 12:48:07 PM PST 24	Feb 04 12:48:12 PM PST 24	171296361 ps
T26	/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.920544979	Feb 04 12:48:38 PM PST 24	Feb 04 12:48:46 PM PST 24	45892786 ps
T20	/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.58262703	Feb 04 12:48:12 PM PST 24	Feb 04 12:48:16 PM PST 24	306093733 ps
T48	/workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.2355646508	Feb 04 12:48:24 PM PST 24	Feb 04 12:48:28 PM PST 24	292139288 ps
T56	/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2191295492	Feb 04 12:48:22 PM PST 24	Feb 04 12:48:25 PM PST 24	68570687 ps
T21	/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1585522797	Feb 04 12:48:16 PM PST 24	Feb 04 12:48:19 PM PST 24	114602371 ps
T60	/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3735911673	Feb 04 12:48:31 PM PST 24	Feb 04 12:48:37 PM PST 24	26074627 ps
T57	/workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.4022355659	Feb 04 12:48:14 PM PST 24	Feb 04 12:48:19 PM PST 24	237904405 ps
T38	/workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3258750425	Feb 04 12:48:30 PM PST 24	Feb 04 12:48:36 PM PST 24	36498930 ps
T61	/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3565498293	Feb 04 12:48:38 PM PST 24	Feb 04 12:48:46 PM PST 24	85029323 ps
T50	/workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.4244034521	Feb 04 12:48:30 PM PST 24	Feb 04 12:48:37 PM PST 24	164375312 ps
T22	/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2186226808	Feb 04 12:48:26 PM PST 24	Feb 04 12:48:29 PM PST 24	70666589 ps
T62	/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3846745396	Feb 04 12:48:31 PM PST 24	Feb 04 12:48:37 PM PST 24	37650743 ps
T23	/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3463782374	Feb 04 12:48:19 PM PST 24	Feb 04 12:48:23 PM PST 24	20832209 ps
T63	/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2673881801	Feb 04 12:48:33 PM PST 24	Feb 04 12:48:39 PM PST 24	43152657 ps
T64	/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.896042074	Feb 04 12:48:38 PM PST 24	Feb 04 12:48:46 PM PST 24	34394074 ps
T39	/workspace/coverage/cover_reg_top/32.usbdev_intr_test.2944497191	Feb 04 12:49:02 PM PST 24	Feb 04 12:49:08 PM PST 24	24748155 ps
T58	/workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2211027313	Feb 04 12:48:54 PM PST 24	Feb 04 12:49:02 PM PST 24	302153987 ps
T51	/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1180365977	Feb 04 12:48:36 PM PST 24	Feb 04 12:48:46 PM PST 24	55095748 ps
T65	/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1051185029	Feb 04 12:48:12 PM PST 24	Feb 04 12:48:14 PM PST 24	32745888 ps
T52	/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3649319042	Feb 04 12:48:15 PM PST 24	Feb 04 12:48:18 PM PST 24	116491623 ps
T40	/workspace/coverage/cover_reg_top/47.usbdev_intr_test.3594097587	Feb 04 12:49:16 PM PST 24	Feb 04 12:49:19 PM PST 24	33387520 ps
T95	/workspace/coverage/cover_reg_top/10.usbdev_intr_test.2628335547	Feb 04 12:48:33 PM PST 24	Feb 04 12:48:39 PM PST 24	36940883 ps
T80	/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.769737327	Feb 04 12:48:14 PM PST 24	Feb 04 12:48:16 PM PST 24	37163436 ps
T85	/workspace/coverage/cover_reg_top/5.usbdev_intr_test.1879206358	Feb 04 12:48:11 PM PST 24	Feb 04 12:48:13 PM PST 24	34394047 ps
T165	/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3053602491	Feb 04 12:48:13 PM PST 24	Feb 04 12:48:15 PM PST 24	65159171 ps
T166	/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2479860011	Feb 04 12:48:24 PM PST 24	Feb 04 12:48:26 PM PST 24	68406174 ps
T81	/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1845415222	Feb 04 12:48:58 PM PST 24	Feb 04 12:49:00 PM PST 24	73312154 ps
T167	/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.504162401	Feb 04 12:48:38 PM PST 24	Feb 04 12:48:47 PM PST 24	57841747 ps
T82	/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3866878503	Feb 04 12:48:18 PM PST 24	Feb 04 12:48:22 PM PST 24	149852673 ps
T83	/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1772619706	Feb 04 12:48:37 PM PST 24	Feb 04 12:48:46 PM PST 24	59298495 ps
T92	/workspace/coverage/cover_reg_top/42.usbdev_intr_test.2413537482	Feb 04 12:49:03 PM PST 24	Feb 04 12:49:08 PM PST 24	34893000 ps
T168	/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.4206577281	Feb 04 12:48:58 PM PST 24	Feb 04 12:49:00 PM PST 24	41243466 ps
T93	/workspace/coverage/cover_reg_top/4.usbdev_intr_test.587185919	Feb 04 12:48:11 PM PST 24	Feb 04 12:48:12 PM PST 24	84354333 ps
T66	/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.4194399376	Feb 04 12:48:17 PM PST 24	Feb 04 12:48:19 PM PST 24	43190980 ps
T169	/workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.44290780	Feb 04 12:48:29 PM PST 24	Feb 04 12:48:34 PM PST 24	41665217 ps
T99	/workspace/coverage/cover_reg_top/34.usbdev_intr_test.3046596235	Feb 04 12:49:06 PM PST 24	Feb 04 12:49:13 PM PST 24	26969378 ps
T94	/workspace/coverage/cover_reg_top/22.usbdev_intr_test.689888153	Feb 04 12:49:08 PM PST 24	Feb 04 12:49:14 PM PST 24	20523915 ps
T170	/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3001594880	Feb 04 12:48:19 PM PST 24	Feb 04 12:48:24 PM PST 24	60478311 ps
T96	/workspace/coverage/cover_reg_top/2.usbdev_intr_test.2759401612	Feb 04 12:48:20 PM PST 24	Feb 04 12:48:23 PM PST 24	27213382 ps
T67	/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.68826170	Feb 04 12:48:19 PM PST 24	Feb 04 12:48:23 PM PST 24	89183014 ps
T171	/workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2196726984	Feb 04 12:48:53 PM PST 24	Feb 04 12:48:56 PM PST 24	35655751 ps
T97	/workspace/coverage/cover_reg_top/28.usbdev_intr_test.3944443966	Feb 04 12:49:04 PM PST 24	Feb 04 12:49:09 PM PST 24	27665832 ps
T172	/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.115360281	Feb 04 12:48:34 PM PST 24	Feb 04 12:48:39 PM PST 24	36633307 ps
T84	/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.981182300	Feb 04 12:48:29 PM PST 24	Feb 04 12:48:35 PM PST 24	210053438 ps
T68	/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1306833557	Feb 04 12:48:34 PM PST 24	Feb 04 12:48:39 PM PST 24	77683441 ps
T30	/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.167236364	Feb 04 12:48:15 PM PST 24	Feb 04 12:48:18 PM PST 24	35666572 ps
T53	/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.228992069	Feb 04 12:48:31 PM PST 24	Feb 04 12:48:39 PM PST 24	210782993 ps
T100	/workspace/coverage/cover_reg_top/14.usbdev_intr_test.1441508889	Feb 04 12:48:30 PM PST 24	Feb 04 12:48:36 PM PST 24	30636217 ps
T173	/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1717568033	Feb 04 12:48:29 PM PST 24	Feb 04 12:48:34 PM PST 24	37856515 ps
T59	/workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.4112841337	Feb 04 12:48:18 PM PST 24	Feb 04 12:48:22 PM PST 24	320689081 ps
T98	/workspace/coverage/cover_reg_top/0.usbdev_intr_test.1657734521	Feb 04 12:48:12 PM PST 24	Feb 04 12:48:13 PM PST 24	21796940 ps
T103	/workspace/coverage/cover_reg_top/33.usbdev_intr_test.2864557475	Feb 04 12:49:03 PM PST 24	Feb 04 12:49:08 PM PST 24	27923330 ps
T174	/workspace/coverage/cover_reg_top/49.usbdev_intr_test.286256672	Feb 04 12:49:17 PM PST 24	Feb 04 12:49:19 PM PST 24	34298157 ps
T54	/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.647446978	Feb 04 12:48:30 PM PST 24	Feb 04 12:48:36 PM PST 24	208546145 ps
T175	/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3668975446	Feb 04 12:48:12 PM PST 24	Feb 04 12:48:14 PM PST 24	50950932 ps
T55	/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2803209581	Feb 04 12:48:27 PM PST 24	Feb 04 12:48:30 PM PST 24	56410037 ps
T86	/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3918916032	Feb 04 12:48:12 PM PST 24	Feb 04 12:48:14 PM PST 24	53209527 ps
T104	/workspace/coverage/cover_reg_top/19.usbdev_intr_test.193029036	Feb 04 12:48:54 PM PST 24	Feb 04 12:48:59 PM PST 24	27968558 ps
T176	/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2270465289	Feb 04 12:48:31 PM PST 24	Feb 04 12:48:38 PM PST 24	184498540 ps
T69	/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3859353383	Feb 04 12:48:15 PM PST 24	Feb 04 12:48:20 PM PST 24	124946844 ps
T87	/workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.4235660644	Feb 04 12:48:30 PM PST 24	Feb 04 12:48:37 PM PST 24	302815837 ps
T177	/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.782698147	Feb 04 12:48:09 PM PST 24	Feb 04 12:48:12 PM PST 24	49076676 ps
T70	/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2251181713	Feb 04 12:48:09 PM PST 24	Feb 04 12:48:11 PM PST 24	46555266 ps
T178	/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3327886801	Feb 04 12:48:36 PM PST 24	Feb 04 12:48:46 PM PST 24	116656999 ps
T105	/workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3569795480	Feb 04 12:48:28 PM PST 24	Feb 04 12:48:34 PM PST 24	127183447 ps
T78	/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2867175229	Feb 04 12:48:31 PM PST 24	Feb 04 12:48:38 PM PST 24	57543462 ps
T179	/workspace/coverage/cover_reg_top/11.usbdev_intr_test.4278949920	Feb 04 12:48:24 PM PST 24	Feb 04 12:48:26 PM PST 24	25191966 ps
T180	/workspace/coverage/cover_reg_top/46.usbdev_intr_test.3857710179	Feb 04 12:49:03 PM PST 24	Feb 04 12:49:08 PM PST 24	90683041 ps
T90	/workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.569424558	Feb 04 12:48:31 PM PST 24	Feb 04 12:48:39 PM PST 24	145654762 ps
T181	/workspace/coverage/cover_reg_top/41.usbdev_intr_test.858101492	Feb 04 12:49:03 PM PST 24	Feb 04 12:49:08 PM PST 24	22460672 ps
T182	/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3831349877	Feb 04 12:48:31 PM PST 24	Feb 04 12:48:38 PM PST 24	72772978 ps
T183	/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2105625593	Feb 04 12:48:18 PM PST 24	Feb 04 12:48:22 PM PST 24	52985614 ps
T184	/workspace/coverage/cover_reg_top/15.usbdev_intr_test.2414435370	Feb 04 12:48:21 PM PST 24	Feb 04 12:48:24 PM PST 24	52107362 ps
T185	/workspace/coverage/cover_reg_top/12.usbdev_intr_test.2258568663	Feb 04 12:48:31 PM PST 24	Feb 04 12:48:37 PM PST 24	52016198 ps
T186	/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3402823747	Feb 04 12:48:24 PM PST 24	Feb 04 12:48:26 PM PST 24	41021797 ps
T187	/workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2353013528	Feb 04 12:48:19 PM PST 24	Feb 04 12:48:24 PM PST 24	354455410 ps
T188	/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2956665876	Feb 04 12:48:58 PM PST 24	Feb 04 12:49:00 PM PST 24	38687434 ps
T79	/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.3545822721	Feb 04 12:48:18 PM PST 24	Feb 04 12:48:23 PM PST 24	236155774 ps
T189	/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2996377375	Feb 04 12:48:46 PM PST 24	Feb 04 12:48:49 PM PST 24	33478852 ps
T190	/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.300720687	Feb 04 12:48:15 PM PST 24	Feb 04 12:48:19 PM PST 24	260688622 ps
T191	/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2570095889	Feb 04 12:48:24 PM PST 24	Feb 04 12:48:29 PM PST 24	312818259 ps
T192	/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.2754531145	Feb 04 12:48:55 PM PST 24	Feb 04 12:49:00 PM PST 24	59447437 ps
T193	/workspace/coverage/cover_reg_top/48.usbdev_intr_test.339443408	Feb 04 12:49:04 PM PST 24	Feb 04 12:49:09 PM PST 24	23692814 ps
T194	/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2181017813	Feb 04 12:48:52 PM PST 24	Feb 04 12:48:56 PM PST 24	73404666 ps
T195	/workspace/coverage/cover_reg_top/37.usbdev_intr_test.2471780608	Feb 04 12:49:06 PM PST 24	Feb 04 12:49:13 PM PST 24	118083780 ps
T196	/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.4278897478	Feb 04 12:48:48 PM PST 24	Feb 04 12:48:52 PM PST 24	210871954 ps
T197	/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3498210930	Feb 04 12:48:24 PM PST 24	Feb 04 12:48:26 PM PST 24	61681089 ps
T31	/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.4116057871	Feb 04 12:48:18 PM PST 24	Feb 04 12:48:21 PM PST 24	32698937 ps
T198	/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.49031574	Feb 04 12:48:20 PM PST 24	Feb 04 12:48:24 PM PST 24	195055461 ps
T199	/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3582959630	Feb 04 12:48:28 PM PST 24	Feb 04 12:48:33 PM PST 24	32886901 ps
T200	/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2647446532	Feb 04 12:48:15 PM PST 24	Feb 04 12:48:18 PM PST 24	82203937 ps
T201	/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.256278854	Feb 04 12:48:20 PM PST 24	Feb 04 12:48:23 PM PST 24	59151665 ps
T202	/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.292463257	Feb 04 12:48:10 PM PST 24	Feb 04 12:48:13 PM PST 24	85347283 ps
T101	/workspace/coverage/cover_reg_top/45.usbdev_intr_test.2513972277	Feb 04 12:49:12 PM PST 24	Feb 04 12:49:16 PM PST 24	61638976 ps
T203	/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2861469830	Feb 04 12:48:09 PM PST 24	Feb 04 12:48:11 PM PST 24	52640112 ps
T204	/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1867865364	Feb 04 12:48:44 PM PST 24	Feb 04 12:48:48 PM PST 24	56636250 ps
T205	/workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2024157736	Feb 04 12:48:50 PM PST 24	Feb 04 12:48:52 PM PST 24	38713201 ps
T206	/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3350086314	Feb 04 12:48:36 PM PST 24	Feb 04 12:48:45 PM PST 24	40656133 ps
T102	/workspace/coverage/cover_reg_top/24.usbdev_intr_test.3183464359	Feb 04 12:49:03 PM PST 24	Feb 04 12:49:08 PM PST 24	28090194 ps
T207	/workspace/coverage/cover_reg_top/1.usbdev_intr_test.3084853782	Feb 04 12:48:14 PM PST 24	Feb 04 12:48:16 PM PST 24	21646802 ps
T208	/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1373713976	Feb 04 12:48:46 PM PST 24	Feb 04 12:48:49 PM PST 24	69241652 ps
T209	/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2948302619	Feb 04 12:48:14 PM PST 24	Feb 04 12:48:17 PM PST 24	39054618 ps
T88	/workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1456132303	Feb 04 12:48:36 PM PST 24	Feb 04 12:48:47 PM PST 24	296440226 ps
T210	/workspace/coverage/cover_reg_top/27.usbdev_intr_test.237789029	Feb 04 12:49:03 PM PST 24	Feb 04 12:49:09 PM PST 24	34706800 ps
T211	/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2440091181	Feb 04 12:48:33 PM PST 24	Feb 04 12:48:39 PM PST 24	77852929 ps
T212	/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1195525301	Feb 04 12:48:06 PM PST 24	Feb 04 12:48:10 PM PST 24	42478498 ps
T213	/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3105353334	Feb 04 12:48:31 PM PST 24	Feb 04 12:48:38 PM PST 24	87611821 ps
T214	/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2994587918	Feb 04 12:48:17 PM PST 24	Feb 04 12:48:21 PM PST 24	86387513 ps
T215	/workspace/coverage/cover_reg_top/13.usbdev_intr_test.3556438902	Feb 04 12:48:18 PM PST 24	Feb 04 12:48:21 PM PST 24	79473669 ps
T216	/workspace/coverage/cover_reg_top/6.usbdev_intr_test.2031682809	Feb 04 12:48:14 PM PST 24	Feb 04 12:48:16 PM PST 24	20362951 ps
T217	/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.501671854	Feb 04 12:48:31 PM PST 24	Feb 04 12:48:39 PM PST 24	235065682 ps
T218	/workspace/coverage/cover_reg_top/7.usbdev_intr_test.3341228712	Feb 04 12:48:18 PM PST 24	Feb 04 12:48:21 PM PST 24	21488831 ps
T219	/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2881564808	Feb 04 12:48:18 PM PST 24	Feb 04 12:48:22 PM PST 24	63450011 ps
T220	/workspace/coverage/cover_reg_top/39.usbdev_intr_test.1836988203	Feb 04 12:49:03 PM PST 24	Feb 04 12:49:09 PM PST 24	25707826 ps
T221	/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3050913136	Feb 04 12:48:15 PM PST 24	Feb 04 12:48:18 PM PST 24	35622865 ps
T222	/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1370136512	Feb 04 12:48:15 PM PST 24	Feb 04 12:48:18 PM PST 24	83512882 ps
T223	/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3213886372	Feb 04 12:48:36 PM PST 24	Feb 04 12:48:46 PM PST 24	40774839 ps
T224	/workspace/coverage/cover_reg_top/26.usbdev_intr_test.1516711800	Feb 04 12:49:01 PM PST 24	Feb 04 12:49:08 PM PST 24	29465635 ps
T91	/workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3179638304	Feb 04 12:48:54 PM PST 24	Feb 04 12:49:01 PM PST 24	242643919 ps
T225	/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1980543857	Feb 04 12:49:03 PM PST 24	Feb 04 12:49:09 PM PST 24	87497455 ps
T226	/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1992604903	Feb 04 12:48:31 PM PST 24	Feb 04 12:48:39 PM PST 24	91155110 ps
T89	/workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.3461889656	Feb 04 12:48:26 PM PST 24	Feb 04 12:48:32 PM PST 24	268929523 ps
T227	/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1517731825	Feb 04 12:48:15 PM PST 24	Feb 04 12:48:19 PM PST 24	71248584 ps
T228	/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3201027429	Feb 04 12:48:44 PM PST 24	Feb 04 12:48:50 PM PST 24	275698599 ps
T229	/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2894992482	Feb 04 12:48:30 PM PST 24	Feb 04 12:48:37 PM PST 24	124138827 ps
T230	/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2656899517	Feb 04 12:48:26 PM PST 24	Feb 04 12:48:29 PM PST 24	56712588 ps
T231	/workspace/coverage/cover_reg_top/30.usbdev_intr_test.1633869957	Feb 04 12:49:01 PM PST 24	Feb 04 12:49:08 PM PST 24	26707034 ps

Test location	/workspace/coverage/default/13.usbdev_pkt_received.2361156625
Short name	T6
Test name
Test status
Simulation time	8373677065 ps
CPU time	7.16 seconds
Started	Feb 04 12:49:58 PM PST 24
Finished	Feb 04 12:50:14 PM PST 24
Peak memory	201940 kb
Host	smart-f8db86a4-18fd-4a31-a5e1-6e3813df5b3c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23611 56625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.2361156625
Directory	/workspace/13.usbdev_pkt_received/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2822778853
Short name	T27
Test name
Test status
Simulation time	144427851 ps
CPU time	2.44 seconds
Started	Feb 04 12:48:30 PM PST 24
Finished	Feb 04 12:48:37 PM PST 24
Peak memory	201920 kb
Host	smart-c4224751-413b-4889-a6da-1ca7dd103ed4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2822778853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.2822778853
Directory	/workspace/2.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_intr_test.1149780235
Short name	T24
Test name
Test status
Simulation time	33074284 ps
CPU time	0.67 seconds
Started	Feb 04 12:48:26 PM PST 24
Finished	Feb 04 12:48:28 PM PST 24
Peak memory	201028 kb
Host	smart-fdd0bc19-d6b4-41e9-92b5-cce5875db337
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1149780235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.1149780235
Directory	/workspace/8.usbdev_intr_test/latest

Test location	/workspace/coverage/default/41.usbdev_smoke.282554538
Short name	T13
Test name
Test status
Simulation time	8367673348 ps
CPU time	8.91 seconds
Started	Feb 04 12:50:13 PM PST 24
Finished	Feb 04 12:50:26 PM PST 24
Peak memory	201908 kb
Host	smart-5056ba62-0a61-47d4-963c-7c721e50a5ac
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28255 4538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.282554538
Directory	/workspace/41.usbdev_smoke/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_intr_test.1768692695
Short name	T36
Test name
Test status
Simulation time	27672127 ps
CPU time	0.67 seconds
Started	Feb 04 12:48:53 PM PST 24
Finished	Feb 04 12:48:57 PM PST 24
Peak memory	200900 kb
Host	smart-d185e182-3906-443a-a7bd-50452de6caef
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1768692695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.1768692695
Directory	/workspace/17.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1585522797
Short name	T21
Test name
Test status
Simulation time	114602371 ps
CPU time	1.55 seconds
Started	Feb 04 12:48:16 PM PST 24
Finished	Feb 04 12:48:19 PM PST 24
Peak memory	201960 kb
Host	smart-74e51ec5-3e62-48de-995b-abb7ea281fc9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1585522797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.1585522797
Directory	/workspace/4.usbdev_tl_errors/latest

Test location	/workspace/coverage/default/1.usbdev_sec_cm.995094285
Short name	T29
Test name
Test status
Simulation time	211947713 ps
CPU time	1.05 seconds
Started	Feb 04 12:49:50 PM PST 24
Finished	Feb 04 12:49:53 PM PST 24
Peak memory	221408 kb
Host	smart-9e97dc3c-447f-438f-b9ff-37383fbea084
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=995094285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.995094285
Directory	/workspace/1.usbdev_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3486121699
Short name	T37
Test name
Test status
Simulation time	70865155 ps
CPU time	1.06 seconds
Started	Feb 04 12:48:24 PM PST 24
Finished	Feb 04 12:48:26 PM PST 24
Peak memory	202028 kb
Host	smart-33b55263-7103-4285-a0b5-4b41b41f83ae
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486121699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.3486121699
Directory	/workspace/10.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/28.usbdev_intr_test.3944443966
Short name	T97
Test name
Test status
Simulation time	27665832 ps
CPU time	0.71 seconds
Started	Feb 04 12:49:04 PM PST 24
Finished	Feb 04 12:49:09 PM PST 24
Peak memory	200988 kb
Host	smart-503be8aa-9fe7-492e-85b3-dbf9d1a65a55
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3944443966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.3944443966
Directory	/workspace/28.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1180365977
Short name	T51
Test name
Test status
Simulation time	55095748 ps
CPU time	1.64 seconds
Started	Feb 04 12:48:36 PM PST 24
Finished	Feb 04 12:48:46 PM PST 24
Peak memory	202076 kb
Host	smart-2f3c27a9-815f-489c-997a-34173e373278
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1180365977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.1180365977
Directory	/workspace/16.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_intr_test.1657734521
Short name	T98
Test name
Test status
Simulation time	21796940 ps
CPU time	0.63 seconds
Started	Feb 04 12:48:12 PM PST 24
Finished	Feb 04 12:48:13 PM PST 24
Peak memory	201060 kb
Host	smart-0197c8ca-c587-447f-b188-c1249ca87f5d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1657734521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.1657734521
Directory	/workspace/0.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.3461889656
Short name	T89
Test name
Test status
Simulation time	268929523 ps
CPU time	4.35 seconds
Started	Feb 04 12:48:26 PM PST 24
Finished	Feb 04 12:48:32 PM PST 24
Peak memory	202000 kb
Host	smart-c6e8ac70-ac84-4733-a170-b37357b62581
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3461889656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.3461889656
Directory	/workspace/12.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.4116057871
Short name	T31
Test name
Test status
Simulation time	32698937 ps
CPU time	0.71 seconds
Started	Feb 04 12:48:18 PM PST 24
Finished	Feb 04 12:48:21 PM PST 24
Peak memory	201724 kb
Host	smart-d3f8bf14-cef9-4bc2-904d-ff4a51a709f4
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116057871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.4116057871
Directory	/workspace/0.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/26.usbdev_intr_test.1516711800
Short name	T224
Test name
Test status
Simulation time	29465635 ps
CPU time	0.73 seconds
Started	Feb 04 12:49:01 PM PST 24
Finished	Feb 04 12:49:08 PM PST 24
Peak memory	200876 kb
Host	smart-a484d55f-8f31-4076-9af5-e70a7188cfb5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1516711800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.1516711800
Directory	/workspace/26.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1456132303
Short name	T88
Test name
Test status
Simulation time	296440226 ps
CPU time	2.89 seconds
Started	Feb 04 12:48:36 PM PST 24
Finished	Feb 04 12:48:47 PM PST 24
Peak memory	201972 kb
Host	smart-bdc73c2d-9c1f-43d8-a50b-1c1d208fe979
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1456132303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.1456132303
Directory	/workspace/9.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.4278897478
Short name	T196
Test name
Test status
Simulation time	210871954 ps
CPU time	2.67 seconds
Started	Feb 04 12:48:48 PM PST 24
Finished	Feb 04 12:48:52 PM PST 24
Peak memory	201948 kb
Host	smart-e7496593-ef24-4a04-b0fb-c46fd8ca7e93
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4278897478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.4278897478
Directory	/workspace/19.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.4019085197
Short name	T19
Test name
Test status
Simulation time	117117272 ps
CPU time	1.39 seconds
Started	Feb 04 12:48:30 PM PST 24
Finished	Feb 04 12:48:36 PM PST 24
Peak memory	210048 kb
Host	smart-4f8e8a04-3a31-49e7-8692-2ad56d8c8d45
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019085197 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_mem_rw_with_rand_reset.4019085197
Directory	/workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.4112841337
Short name	T59
Test name
Test status
Simulation time	320689081 ps
CPU time	2.74 seconds
Started	Feb 04 12:48:18 PM PST 24
Finished	Feb 04 12:48:22 PM PST 24
Peak memory	201940 kb
Host	smart-378aa75a-968d-453e-bc51-80d11da5ba88
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=4112841337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.4112841337
Directory	/workspace/3.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3258750425
Short name	T38
Test name
Test status
Simulation time	36498930 ps
CPU time	0.73 seconds
Started	Feb 04 12:48:30 PM PST 24
Finished	Feb 04 12:48:36 PM PST 24
Peak memory	201728 kb
Host	smart-11263296-e57d-4d84-85be-3383b6dc3553
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258750425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.3258750425
Directory	/workspace/1.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/default/10.usbdev_pkt_received.3102752908
Short name	T45
Test name
Test status
Simulation time	8402981487 ps
CPU time	7.54 seconds
Started	Feb 04 12:49:57 PM PST 24
Finished	Feb 04 12:50:08 PM PST 24
Peak memory	201700 kb
Host	smart-20cfb605-7a52-45f9-93c7-c513a03c9c58
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31027 52908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.3102752908
Directory	/workspace/10.usbdev_pkt_received/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.4057175595
Short name	T32
Test name
Test status
Simulation time	302277222 ps
CPU time	4.84 seconds
Started	Feb 04 12:48:10 PM PST 24
Finished	Feb 04 12:48:15 PM PST 24
Peak memory	202092 kb
Host	smart-fc406ffd-5f6b-4385-9e0b-29c8d9ad5ed7
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057175595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.4057175595
Directory	/workspace/0.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1195525301
Short name	T212
Test name
Test status
Simulation time	42478498 ps
CPU time	1.33 seconds
Started	Feb 04 12:48:06 PM PST 24
Finished	Feb 04 12:48:10 PM PST 24
Peak memory	201972 kb
Host	smart-78ccab3d-f1e9-412c-9759-622f111f85dd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1195525301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.1195525301
Directory	/workspace/1.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2861469830
Short name	T203
Test name
Test status
Simulation time	52640112 ps
CPU time	1.61 seconds
Started	Feb 04 12:48:09 PM PST 24
Finished	Feb 04 12:48:11 PM PST 24
Peak memory	210204 kb
Host	smart-ea23a6bf-e4b7-478a-9d60-5b68f9df1519
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861469830 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_mem_rw_with_rand_reset.2861469830
Directory	/workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1051185029
Short name	T65
Test name
Test status
Simulation time	32745888 ps
CPU time	0.97 seconds
Started	Feb 04 12:48:12 PM PST 24
Finished	Feb 04 12:48:14 PM PST 24
Peak memory	202032 kb
Host	smart-d730676a-2f26-4064-bffa-c5a9e0f41a4e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051185029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.1051185029
Directory	/workspace/0.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1370136512
Short name	T222
Test name
Test status
Simulation time	83512882 ps
CPU time	1.33 seconds
Started	Feb 04 12:48:15 PM PST 24
Finished	Feb 04 12:48:18 PM PST 24
Peak memory	201932 kb
Host	smart-3de027d5-228a-4a7a-ae12-f1eda9447e5d
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1370136512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.1370136512
Directory	/workspace/0.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.58262703
Short name	T20
Test name
Test status
Simulation time	306093733 ps
CPU time	2.44 seconds
Started	Feb 04 12:48:12 PM PST 24
Finished	Feb 04 12:48:16 PM PST 24
Peak memory	201848 kb
Host	smart-0808769d-9ecc-43b3-b34a-47c527299511
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=58262703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.58262703
Directory	/workspace/0.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.49031574
Short name	T198
Test name
Test status
Simulation time	195055461 ps
CPU time	1.14 seconds
Started	Feb 04 12:48:20 PM PST 24
Finished	Feb 04 12:48:24 PM PST 24
Peak memory	201796 kb
Host	smart-e55aa17a-24eb-448e-bacc-44f4ea4cc645
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49031574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr _outstanding.49031574
Directory	/workspace/0.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.501671854
Short name	T217
Test name
Test status
Simulation time	235065682 ps
CPU time	2.45 seconds
Started	Feb 04 12:48:31 PM PST 24
Finished	Feb 04 12:48:39 PM PST 24
Peak memory	202056 kb
Host	smart-d86a5281-f8f3-4e94-9525-cfaeaa75f79e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=501671854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.501671854
Directory	/workspace/0.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2570095889
Short name	T191
Test name
Test status
Simulation time	312818259 ps
CPU time	3.33 seconds
Started	Feb 04 12:48:24 PM PST 24
Finished	Feb 04 12:48:29 PM PST 24
Peak memory	202008 kb
Host	smart-d4ac4585-40b5-4ce9-b873-e973da10b07f
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570095889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.2570095889
Directory	/workspace/1.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2948302619
Short name	T209
Test name
Test status
Simulation time	39054618 ps
CPU time	1.07 seconds
Started	Feb 04 12:48:14 PM PST 24
Finished	Feb 04 12:48:17 PM PST 24
Peak memory	201924 kb
Host	smart-be60bc7c-0c64-473d-bd71-4ab222298c01
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948302619 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_mem_rw_with_rand_reset.2948302619
Directory	/workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2647446532
Short name	T200
Test name
Test status
Simulation time	82203937 ps
CPU time	1.09 seconds
Started	Feb 04 12:48:15 PM PST 24
Finished	Feb 04 12:48:18 PM PST 24
Peak memory	202084 kb
Host	smart-284e7ca5-644b-48e4-a81b-d72d103abdb3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647446532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.2647446532
Directory	/workspace/1.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_intr_test.3084853782
Short name	T207
Test name
Test status
Simulation time	21646802 ps
CPU time	0.61 seconds
Started	Feb 04 12:48:14 PM PST 24
Finished	Feb 04 12:48:16 PM PST 24
Peak memory	201032 kb
Host	smart-946b7c3b-0856-48fa-ac00-3864e1a13671
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3084853782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.3084853782
Directory	/workspace/1.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2251181713
Short name	T70
Test name
Test status
Simulation time	46555266 ps
CPU time	1.32 seconds
Started	Feb 04 12:48:09 PM PST 24
Finished	Feb 04 12:48:11 PM PST 24
Peak memory	201912 kb
Host	smart-75a53b22-d372-42a2-9d7f-f974fae1c459
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2251181713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.2251181713
Directory	/workspace/1.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2353013528
Short name	T187
Test name
Test status
Simulation time	354455410 ps
CPU time	2.55 seconds
Started	Feb 04 12:48:19 PM PST 24
Finished	Feb 04 12:48:24 PM PST 24
Peak memory	201764 kb
Host	smart-55e2511e-b8ca-48f7-9cac-16a5aec2eb1a
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2353013528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.2353013528
Directory	/workspace/1.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2479860011
Short name	T166
Test name
Test status
Simulation time	68406174 ps
CPU time	1.1 seconds
Started	Feb 04 12:48:24 PM PST 24
Finished	Feb 04 12:48:26 PM PST 24
Peak memory	201972 kb
Host	smart-829244fc-e9fa-4086-8ebb-d8ab82d0d400
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479860011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_c sr_outstanding.2479860011
Directory	/workspace/1.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3399580864
Short name	T25
Test name
Test status
Simulation time	171296361 ps
CPU time	2.63 seconds
Started	Feb 04 12:48:07 PM PST 24
Finished	Feb 04 12:48:12 PM PST 24
Peak memory	202012 kb
Host	smart-8326b5cc-7e2f-49c5-97f9-b53f7e6fef45
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3399580864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.3399580864
Directory	/workspace/1.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2881564808
Short name	T219
Test name
Test status
Simulation time	63450011 ps
CPU time	1.48 seconds
Started	Feb 04 12:48:18 PM PST 24
Finished	Feb 04 12:48:22 PM PST 24
Peak memory	202024 kb
Host	smart-29cbb201-0ff4-4da7-aaf4-36c90a2daa62
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881564808 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_mem_rw_with_rand_reset.2881564808
Directory	/workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_intr_test.2628335547
Short name	T95
Test name
Test status
Simulation time	36940883 ps
CPU time	0.65 seconds
Started	Feb 04 12:48:33 PM PST 24
Finished	Feb 04 12:48:39 PM PST 24
Peak memory	201052 kb
Host	smart-be435f88-6a41-420c-a05e-db0ea2bb840f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2628335547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.2628335547
Directory	/workspace/10.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3327886801
Short name	T178
Test name
Test status
Simulation time	116656999 ps
CPU time	1.38 seconds
Started	Feb 04 12:48:36 PM PST 24
Finished	Feb 04 12:48:46 PM PST 24
Peak memory	201912 kb
Host	smart-7551d9a8-96f2-44ad-8282-d103c87dfb5b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327886801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_ csr_outstanding.3327886801
Directory	/workspace/10.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1992604903
Short name	T226
Test name
Test status
Simulation time	91155110 ps
CPU time	2.92 seconds
Started	Feb 04 12:48:31 PM PST 24
Finished	Feb 04 12:48:39 PM PST 24
Peak memory	201964 kb
Host	smart-1e821be3-2566-404d-9469-1e7f80ba6696
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1992604903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.1992604903
Directory	/workspace/10.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.4235660644
Short name	T87
Test name
Test status
Simulation time	302815837 ps
CPU time	2.97 seconds
Started	Feb 04 12:48:30 PM PST 24
Finished	Feb 04 12:48:37 PM PST 24
Peak memory	201968 kb
Host	smart-cfaf1dfe-71a3-4f64-a4a2-e4a7d72f063a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=4235660644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.4235660644
Directory	/workspace/10.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2186226808
Short name	T22
Test name
Test status
Simulation time	70666589 ps
CPU time	1.54 seconds
Started	Feb 04 12:48:26 PM PST 24
Finished	Feb 04 12:48:29 PM PST 24
Peak memory	202144 kb
Host	smart-cde10f08-a13f-4c51-ab62-8cee6dd24300
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186226808 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_mem_rw_with_rand_reset.2186226808
Directory	/workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3582959630
Short name	T199
Test name
Test status
Simulation time	32886901 ps
CPU time	0.92 seconds
Started	Feb 04 12:48:28 PM PST 24
Finished	Feb 04 12:48:33 PM PST 24
Peak memory	201840 kb
Host	smart-063c7a7d-4b9e-4c91-9eea-1067e017a8ba
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582959630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.3582959630
Directory	/workspace/11.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_intr_test.4278949920
Short name	T179
Test name
Test status
Simulation time	25191966 ps
CPU time	0.65 seconds
Started	Feb 04 12:48:24 PM PST 24
Finished	Feb 04 12:48:26 PM PST 24
Peak memory	200892 kb
Host	smart-6dc573ed-3c84-4a0b-b7ce-15599d8b9386
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4278949920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.4278949920
Directory	/workspace/11.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3831349877
Short name	T182
Test name
Test status
Simulation time	72772978 ps
CPU time	1.43 seconds
Started	Feb 04 12:48:31 PM PST 24
Finished	Feb 04 12:48:38 PM PST 24
Peak memory	201924 kb
Host	smart-4b6edae3-a066-4d15-982b-11150bb32fca
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831349877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_ csr_outstanding.3831349877
Directory	/workspace/11.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.228992069
Short name	T53
Test name
Test status
Simulation time	210782993 ps
CPU time	2.39 seconds
Started	Feb 04 12:48:31 PM PST 24
Finished	Feb 04 12:48:39 PM PST 24
Peak memory	201952 kb
Host	smart-f6ce83c1-ed4b-4d36-9c9b-ae757415686e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=228992069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.228992069
Directory	/workspace/11.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3350086314
Short name	T206
Test name
Test status
Simulation time	40656133 ps
CPU time	0.77 seconds
Started	Feb 04 12:48:36 PM PST 24
Finished	Feb 04 12:48:45 PM PST 24
Peak memory	201744 kb
Host	smart-6e129cac-856d-4c6c-b9fe-7e57927c740b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350086314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.3350086314
Directory	/workspace/12.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_intr_test.2258568663
Short name	T185
Test name
Test status
Simulation time	52016198 ps
CPU time	0.71 seconds
Started	Feb 04 12:48:31 PM PST 24
Finished	Feb 04 12:48:37 PM PST 24
Peak memory	200860 kb
Host	smart-117b0f47-e039-4181-835a-ed9f870ca173
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2258568663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.2258568663
Directory	/workspace/12.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.256278854
Short name	T201
Test name
Test status
Simulation time	59151665 ps
CPU time	1.33 seconds
Started	Feb 04 12:48:20 PM PST 24
Finished	Feb 04 12:48:23 PM PST 24
Peak memory	202048 kb
Host	smart-d49b31d5-c23d-473d-b9dc-f95ac53aab00
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256278854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_c sr_outstanding.256278854
Directory	/workspace/12.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3213886372
Short name	T223
Test name
Test status
Simulation time	40774839 ps
CPU time	1.14 seconds
Started	Feb 04 12:48:36 PM PST 24
Finished	Feb 04 12:48:46 PM PST 24
Peak memory	201976 kb
Host	smart-507faf3c-2909-4451-9a64-e4e71990508c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3213886372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.3213886372
Directory	/workspace/12.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3158960120
Short name	T17
Test name
Test status
Simulation time	46317780 ps
CPU time	1.9 seconds
Started	Feb 04 12:48:24 PM PST 24
Finished	Feb 04 12:48:27 PM PST 24
Peak memory	210276 kb
Host	smart-4a674c1f-f23a-44b3-974b-b40860630210
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158960120 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_mem_rw_with_rand_reset.3158960120
Directory	/workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.920544979
Short name	T26
Test name
Test status
Simulation time	45892786 ps
CPU time	0.82 seconds
Started	Feb 04 12:48:38 PM PST 24
Finished	Feb 04 12:48:46 PM PST 24
Peak memory	201832 kb
Host	smart-983f62b9-d059-4612-919f-c696ba56c801
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920544979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.920544979
Directory	/workspace/13.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_intr_test.3556438902
Short name	T215
Test name
Test status
Simulation time	79473669 ps
CPU time	0.65 seconds
Started	Feb 04 12:48:18 PM PST 24
Finished	Feb 04 12:48:21 PM PST 24
Peak memory	200976 kb
Host	smart-cd618bbd-c842-4ef6-bf0d-796ff7825929
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3556438902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.3556438902
Directory	/workspace/13.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1717568033
Short name	T173
Test name
Test status
Simulation time	37856515 ps
CPU time	1 seconds
Started	Feb 04 12:48:29 PM PST 24
Finished	Feb 04 12:48:34 PM PST 24
Peak memory	201992 kb
Host	smart-a50e98ef-e0b6-47e4-8e71-964024fca4b2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717568033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_ csr_outstanding.1717568033
Directory	/workspace/13.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.647446978
Short name	T54
Test name
Test status
Simulation time	208546145 ps
CPU time	2.66 seconds
Started	Feb 04 12:48:30 PM PST 24
Finished	Feb 04 12:48:36 PM PST 24
Peak memory	201924 kb
Host	smart-69164377-eac2-4d24-9187-8c6b77611144
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=647446978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.647446978
Directory	/workspace/13.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.4244034521
Short name	T50
Test name
Test status
Simulation time	164375312 ps
CPU time	2.39 seconds
Started	Feb 04 12:48:30 PM PST 24
Finished	Feb 04 12:48:37 PM PST 24
Peak memory	201844 kb
Host	smart-affca3aa-b268-48a8-b503-333e63f133e1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=4244034521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.4244034521
Directory	/workspace/13.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.504162401
Short name	T167
Test name
Test status
Simulation time	57841747 ps
CPU time	1.33 seconds
Started	Feb 04 12:48:38 PM PST 24
Finished	Feb 04 12:48:47 PM PST 24
Peak memory	218444 kb
Host	smart-0efb8f75-6862-4c81-be7e-045d495e0edd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504162401 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_mem_rw_with_rand_reset.504162401
Directory	/workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.896042074
Short name	T64
Test name
Test status
Simulation time	34394074 ps
CPU time	0.91 seconds
Started	Feb 04 12:48:38 PM PST 24
Finished	Feb 04 12:48:46 PM PST 24
Peak memory	201836 kb
Host	smart-afeeb280-8114-4b38-b437-be0a33e232cd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896042074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.896042074
Directory	/workspace/14.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_intr_test.1441508889
Short name	T100
Test name
Test status
Simulation time	30636217 ps
CPU time	0.61 seconds
Started	Feb 04 12:48:30 PM PST 24
Finished	Feb 04 12:48:36 PM PST 24
Peak memory	200956 kb
Host	smart-a183fb26-413a-4ea1-8a90-308adb9efadf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1441508889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.1441508889
Directory	/workspace/14.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3846745396
Short name	T62
Test name
Test status
Simulation time	37650743 ps
CPU time	1.03 seconds
Started	Feb 04 12:48:31 PM PST 24
Finished	Feb 04 12:48:37 PM PST 24
Peak memory	201892 kb
Host	smart-829099e9-daf8-4435-98c8-43b1d10db1e6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846745396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_ csr_outstanding.3846745396
Directory	/workspace/14.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2894992482
Short name	T229
Test name
Test status
Simulation time	124138827 ps
CPU time	1.72 seconds
Started	Feb 04 12:48:30 PM PST 24
Finished	Feb 04 12:48:37 PM PST 24
Peak memory	201996 kb
Host	smart-91fbd489-5a33-4358-8852-ae9666064a57
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2894992482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.2894992482
Directory	/workspace/14.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.2355646508
Short name	T48
Test name
Test status
Simulation time	292139288 ps
CPU time	3 seconds
Started	Feb 04 12:48:24 PM PST 24
Finished	Feb 04 12:48:28 PM PST 24
Peak memory	202008 kb
Host	smart-f1f00f61-8bcc-449f-bbe0-eb9301de6c2f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2355646508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.2355646508
Directory	/workspace/14.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1772619706
Short name	T83
Test name
Test status
Simulation time	59298495 ps
CPU time	1.37 seconds
Started	Feb 04 12:48:37 PM PST 24
Finished	Feb 04 12:48:46 PM PST 24
Peak memory	202180 kb
Host	smart-8e07e1df-8539-4436-a208-b2ac570c64c7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772619706 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_mem_rw_with_rand_reset.1772619706
Directory	/workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3565498293
Short name	T61
Test name
Test status
Simulation time	85029323 ps
CPU time	0.85 seconds
Started	Feb 04 12:48:38 PM PST 24
Finished	Feb 04 12:48:46 PM PST 24
Peak memory	201740 kb
Host	smart-ae6a9b24-b4e8-496b-b88d-eef05164b00b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565498293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.3565498293
Directory	/workspace/15.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_intr_test.2414435370
Short name	T184
Test name
Test status
Simulation time	52107362 ps
CPU time	0.64 seconds
Started	Feb 04 12:48:21 PM PST 24
Finished	Feb 04 12:48:24 PM PST 24
Peak memory	201076 kb
Host	smart-b2e8857e-4469-44c2-ba8e-97791aa3b0ae
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2414435370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.2414435370
Directory	/workspace/15.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.115360281
Short name	T172
Test name
Test status
Simulation time	36633307 ps
CPU time	1.02 seconds
Started	Feb 04 12:48:34 PM PST 24
Finished	Feb 04 12:48:39 PM PST 24
Peak memory	201928 kb
Host	smart-626134cf-22ff-469d-a068-d0497249f614
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115360281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_c sr_outstanding.115360281
Directory	/workspace/15.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2803209581
Short name	T55
Test name
Test status
Simulation time	56410037 ps
CPU time	1.64 seconds
Started	Feb 04 12:48:27 PM PST 24
Finished	Feb 04 12:48:30 PM PST 24
Peak memory	202064 kb
Host	smart-d6b97fa9-110f-4fb8-a358-4913fbfa5e71
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2803209581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.2803209581
Directory	/workspace/15.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1373713976
Short name	T208
Test name
Test status
Simulation time	69241652 ps
CPU time	0.99 seconds
Started	Feb 04 12:48:46 PM PST 24
Finished	Feb 04 12:48:49 PM PST 24
Peak memory	202060 kb
Host	smart-ae5c1ddf-91d3-4cca-8845-f3b5e3989b2b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373713976 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_mem_rw_with_rand_reset.1373713976
Directory	/workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2024157736
Short name	T205
Test name
Test status
Simulation time	38713201 ps
CPU time	1.02 seconds
Started	Feb 04 12:48:50 PM PST 24
Finished	Feb 04 12:48:52 PM PST 24
Peak memory	202028 kb
Host	smart-1252996d-2648-4903-a7ad-264e98360dd4
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024157736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.2024157736
Directory	/workspace/16.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_intr_test.989133339
Short name	T35
Test name
Test status
Simulation time	41273610 ps
CPU time	0.7 seconds
Started	Feb 04 12:48:43 PM PST 24
Finished	Feb 04 12:48:48 PM PST 24
Peak memory	201088 kb
Host	smart-dc906f47-46cb-40e2-b817-3da37deedbd4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=989133339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.989133339
Directory	/workspace/16.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.4206577281
Short name	T168
Test name
Test status
Simulation time	41243466 ps
CPU time	0.95 seconds
Started	Feb 04 12:48:58 PM PST 24
Finished	Feb 04 12:49:00 PM PST 24
Peak memory	201896 kb
Host	smart-0274a3d9-c931-4ee7-b514-58b6a85ce474
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206577281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_ csr_outstanding.4206577281
Directory	/workspace/16.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3569795480
Short name	T105
Test name
Test status
Simulation time	127183447 ps
CPU time	2.44 seconds
Started	Feb 04 12:48:28 PM PST 24
Finished	Feb 04 12:48:34 PM PST 24
Peak memory	202040 kb
Host	smart-8a22d303-de54-41b8-801f-daa9f80f599a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3569795480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.3569795480
Directory	/workspace/16.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2196726984
Short name	T171
Test name
Test status
Simulation time	35655751 ps
CPU time	0.89 seconds
Started	Feb 04 12:48:53 PM PST 24
Finished	Feb 04 12:48:56 PM PST 24
Peak memory	202068 kb
Host	smart-28dace58-406b-4c5f-9fef-524fe8b19010
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196726984 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_mem_rw_with_rand_reset.2196726984
Directory	/workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2956665876
Short name	T188
Test name
Test status
Simulation time	38687434 ps
CPU time	0.79 seconds
Started	Feb 04 12:48:58 PM PST 24
Finished	Feb 04 12:49:00 PM PST 24
Peak memory	201640 kb
Host	smart-6fdcab98-1b2d-4dcf-820c-531398a830be
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956665876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.2956665876
Directory	/workspace/17.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2181017813
Short name	T194
Test name
Test status
Simulation time	73404666 ps
CPU time	1.1 seconds
Started	Feb 04 12:48:52 PM PST 24
Finished	Feb 04 12:48:56 PM PST 24
Peak memory	201952 kb
Host	smart-7da690ca-0d0a-40c2-9f94-d2f76e17d7d3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181017813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_ csr_outstanding.2181017813
Directory	/workspace/17.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3201027429
Short name	T228
Test name
Test status
Simulation time	275698599 ps
CPU time	2.99 seconds
Started	Feb 04 12:48:44 PM PST 24
Finished	Feb 04 12:48:50 PM PST 24
Peak memory	202036 kb
Host	smart-b5a784d2-eaa7-442c-b4e4-5881561336b8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3201027429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.3201027429
Directory	/workspace/17.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1867865364
Short name	T204
Test name
Test status
Simulation time	56636250 ps
CPU time	1.36 seconds
Started	Feb 04 12:48:44 PM PST 24
Finished	Feb 04 12:48:48 PM PST 24
Peak memory	201996 kb
Host	smart-bb9124fe-b153-4b2c-8161-00211be819e9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867865364 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_mem_rw_with_rand_reset.1867865364
Directory	/workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2996377375
Short name	T189
Test name
Test status
Simulation time	33478852 ps
CPU time	0.86 seconds
Started	Feb 04 12:48:46 PM PST 24
Finished	Feb 04 12:48:49 PM PST 24
Peak memory	201708 kb
Host	smart-f887579f-90a9-4a92-aa35-c499270c2c86
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996377375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.2996377375
Directory	/workspace/18.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1845415222
Short name	T81
Test name
Test status
Simulation time	73312154 ps
CPU time	0.98 seconds
Started	Feb 04 12:48:58 PM PST 24
Finished	Feb 04 12:49:00 PM PST 24
Peak memory	202068 kb
Host	smart-67d63ac8-82f0-4e64-8d06-e430e5276017
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845415222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_ csr_outstanding.1845415222
Directory	/workspace/18.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.2754531145
Short name	T192
Test name
Test status
Simulation time	59447437 ps
CPU time	1.75 seconds
Started	Feb 04 12:48:55 PM PST 24
Finished	Feb 04 12:49:00 PM PST 24
Peak memory	202024 kb
Host	smart-ee951e87-3439-448c-b72c-1733b38b9bec
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2754531145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.2754531145
Directory	/workspace/18.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3179638304
Short name	T91
Test name
Test status
Simulation time	242643919 ps
CPU time	4.14 seconds
Started	Feb 04 12:48:54 PM PST 24
Finished	Feb 04 12:49:01 PM PST 24
Peak memory	201924 kb
Host	smart-b28a0c2a-a6f9-4606-8a1e-04fc818830aa
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3179638304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.3179638304
Directory	/workspace/18.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.955401202
Short name	T47
Test name
Test status
Simulation time	143727489 ps
CPU time	0.91 seconds
Started	Feb 04 12:48:46 PM PST 24
Finished	Feb 04 12:48:49 PM PST 24
Peak memory	201752 kb
Host	smart-ee5a2c87-a81d-4f67-a181-7af0c96150cf
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955401202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.955401202
Directory	/workspace/19.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_intr_test.193029036
Short name	T104
Test name
Test status
Simulation time	27968558 ps
CPU time	0.66 seconds
Started	Feb 04 12:48:54 PM PST 24
Finished	Feb 04 12:48:59 PM PST 24
Peak memory	200900 kb
Host	smart-7f11a592-b8f2-437a-a005-f1bab98102e4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=193029036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.193029036
Directory	/workspace/19.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1980543857
Short name	T225
Test name
Test status
Simulation time	87497455 ps
CPU time	1.11 seconds
Started	Feb 04 12:49:03 PM PST 24
Finished	Feb 04 12:49:09 PM PST 24
Peak memory	202008 kb
Host	smart-355dd4e8-632e-431d-bc4f-fe28d648fc98
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980543857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_ csr_outstanding.1980543857
Directory	/workspace/19.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2211027313
Short name	T58
Test name
Test status
Simulation time	302153987 ps
CPU time	4.29 seconds
Started	Feb 04 12:48:54 PM PST 24
Finished	Feb 04 12:49:02 PM PST 24
Peak memory	201984 kb
Host	smart-56b130e5-e170-4a9a-8795-61ab8507fb04
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2211027313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.2211027313
Directory	/workspace/19.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.981182300
Short name	T84
Test name
Test status
Simulation time	210053438 ps
CPU time	2 seconds
Started	Feb 04 12:48:29 PM PST 24
Finished	Feb 04 12:48:35 PM PST 24
Peak memory	201872 kb
Host	smart-dc2bb74e-2afb-44f8-b2ab-73aab3260d39
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981182300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.981182300
Directory	/workspace/2.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.769737327
Short name	T80
Test name
Test status
Simulation time	37163436 ps
CPU time	0.74 seconds
Started	Feb 04 12:48:14 PM PST 24
Finished	Feb 04 12:48:16 PM PST 24
Peak memory	201720 kb
Host	smart-fe820c01-a47e-4d17-a471-4781e8815ec0
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769737327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.769737327
Directory	/workspace/2.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3463782374
Short name	T23
Test name
Test status
Simulation time	20832209 ps
CPU time	0.87 seconds
Started	Feb 04 12:48:19 PM PST 24
Finished	Feb 04 12:48:23 PM PST 24
Peak memory	201984 kb
Host	smart-c0b60b2e-3eac-44e3-982d-3ced0531c91a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463782374 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_mem_rw_with_rand_reset.3463782374
Directory	/workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_intr_test.2759401612
Short name	T96
Test name
Test status
Simulation time	27213382 ps
CPU time	0.63 seconds
Started	Feb 04 12:48:20 PM PST 24
Finished	Feb 04 12:48:23 PM PST 24
Peak memory	200884 kb
Host	smart-8d68aead-90a5-4962-a1dd-4a648675b385
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2759401612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.2759401612
Directory	/workspace/2.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.68826170
Short name	T67
Test name
Test status
Simulation time	89183014 ps
CPU time	1.41 seconds
Started	Feb 04 12:48:19 PM PST 24
Finished	Feb 04 12:48:23 PM PST 24
Peak memory	201844 kb
Host	smart-77351179-1dc6-4907-af65-1b0ae9b43df6
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=68826170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.68826170
Directory	/workspace/2.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2237573493
Short name	T14
Test name
Test status
Simulation time	97188332 ps
CPU time	2.25 seconds
Started	Feb 04 12:48:22 PM PST 24
Finished	Feb 04 12:48:27 PM PST 24
Peak memory	201836 kb
Host	smart-49188958-4caa-407e-b7a3-00f774a99977
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2237573493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.2237573493
Directory	/workspace/2.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.44290780
Short name	T169
Test name
Test status
Simulation time	41665217 ps
CPU time	1.02 seconds
Started	Feb 04 12:48:29 PM PST 24
Finished	Feb 04 12:48:34 PM PST 24
Peak memory	201940 kb
Host	smart-7b23dcd8-47f6-4213-bc59-d5d0ab65c943
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44290780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr _outstanding.44290780
Directory	/workspace/2.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.3545822721
Short name	T79
Test name
Test status
Simulation time	236155774 ps
CPU time	2.54 seconds
Started	Feb 04 12:48:18 PM PST 24
Finished	Feb 04 12:48:23 PM PST 24
Peak memory	201988 kb
Host	smart-b634e53a-3591-4637-8fd7-add7a25541b3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3545822721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.3545822721
Directory	/workspace/2.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/22.usbdev_intr_test.689888153
Short name	T94
Test name
Test status
Simulation time	20523915 ps
CPU time	0.61 seconds
Started	Feb 04 12:49:08 PM PST 24
Finished	Feb 04 12:49:14 PM PST 24
Peak memory	200952 kb
Host	smart-67028dce-c5eb-40ce-8480-2546620b765d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=689888153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.689888153
Directory	/workspace/22.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.usbdev_intr_test.3183464359
Short name	T102
Test name
Test status
Simulation time	28090194 ps
CPU time	0.66 seconds
Started	Feb 04 12:49:03 PM PST 24
Finished	Feb 04 12:49:08 PM PST 24
Peak memory	200976 kb
Host	smart-84f2952e-4d84-41ab-b2ea-f5d4542f780a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3183464359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.3183464359
Directory	/workspace/24.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.usbdev_intr_test.237789029
Short name	T210
Test name
Test status
Simulation time	34706800 ps
CPU time	0.67 seconds
Started	Feb 04 12:49:03 PM PST 24
Finished	Feb 04 12:49:09 PM PST 24
Peak memory	201016 kb
Host	smart-011d2066-97ff-4aa3-a02e-c3ac32db96d1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=237789029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.237789029
Directory	/workspace/27.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2270465289
Short name	T176
Test name
Test status
Simulation time	184498540 ps
CPU time	1.95 seconds
Started	Feb 04 12:48:31 PM PST 24
Finished	Feb 04 12:48:38 PM PST 24
Peak memory	201976 kb
Host	smart-04e308dc-770d-462c-8c0d-ddd9cb76c183
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270465289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.2270465289
Directory	/workspace/3.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3918916032
Short name	T86
Test name
Test status
Simulation time	53209527 ps
CPU time	1.31 seconds
Started	Feb 04 12:48:12 PM PST 24
Finished	Feb 04 12:48:14 PM PST 24
Peak memory	202144 kb
Host	smart-c2f55c28-2421-4e5c-993e-56e3bc8ba483
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918916032 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_mem_rw_with_rand_reset.3918916032
Directory	/workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3735911673
Short name	T60
Test name
Test status
Simulation time	26074627 ps
CPU time	0.75 seconds
Started	Feb 04 12:48:31 PM PST 24
Finished	Feb 04 12:48:37 PM PST 24
Peak memory	201868 kb
Host	smart-17a4a0fb-814a-4eae-80f9-af5d7d267263
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735911673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.3735911673
Directory	/workspace/3.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.4194399376
Short name	T66
Test name
Test status
Simulation time	43190980 ps
CPU time	1.35 seconds
Started	Feb 04 12:48:17 PM PST 24
Finished	Feb 04 12:48:19 PM PST 24
Peak memory	201936 kb
Host	smart-25c216e5-e944-4731-abcb-7ed0e153704e
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4194399376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.4194399376
Directory	/workspace/3.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2899667963
Short name	T15
Test name
Test status
Simulation time	86206873 ps
CPU time	2.21 seconds
Started	Feb 04 12:48:19 PM PST 24
Finished	Feb 04 12:48:23 PM PST 24
Peak memory	201764 kb
Host	smart-1eb74839-d7e6-4816-bd1d-11fc1069d733
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2899667963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.2899667963
Directory	/workspace/3.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3105353334
Short name	T213
Test name
Test status
Simulation time	87611821 ps
CPU time	1.08 seconds
Started	Feb 04 12:48:31 PM PST 24
Finished	Feb 04 12:48:38 PM PST 24
Peak memory	202004 kb
Host	smart-a8770bc4-a3af-46ea-bc76-c6221218a017
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105353334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_c sr_outstanding.3105353334
Directory	/workspace/3.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2867175229
Short name	T78
Test name
Test status
Simulation time	57543462 ps
CPU time	1.58 seconds
Started	Feb 04 12:48:31 PM PST 24
Finished	Feb 04 12:48:38 PM PST 24
Peak memory	202084 kb
Host	smart-0df166a4-c12f-4961-8695-d6cb1db42c6e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2867175229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.2867175229
Directory	/workspace/3.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/30.usbdev_intr_test.1633869957
Short name	T231
Test name
Test status
Simulation time	26707034 ps
CPU time	0.6 seconds
Started	Feb 04 12:49:01 PM PST 24
Finished	Feb 04 12:49:08 PM PST 24
Peak memory	201148 kb
Host	smart-d6e9f64b-21dc-4682-ab74-f535e62302cd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1633869957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.1633869957
Directory	/workspace/30.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.usbdev_intr_test.2944497191
Short name	T39
Test name
Test status
Simulation time	24748155 ps
CPU time	0.64 seconds
Started	Feb 04 12:49:02 PM PST 24
Finished	Feb 04 12:49:08 PM PST 24
Peak memory	200964 kb
Host	smart-bdd24374-0457-4553-8160-9350860947e6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2944497191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.2944497191
Directory	/workspace/32.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.usbdev_intr_test.2864557475
Short name	T103
Test name
Test status
Simulation time	27923330 ps
CPU time	0.66 seconds
Started	Feb 04 12:49:03 PM PST 24
Finished	Feb 04 12:49:08 PM PST 24
Peak memory	201036 kb
Host	smart-e77ca583-7a80-4302-835c-3b62898e0cbc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2864557475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.2864557475
Directory	/workspace/33.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.usbdev_intr_test.3046596235
Short name	T99
Test name
Test status
Simulation time	26969378 ps
CPU time	0.66 seconds
Started	Feb 04 12:49:06 PM PST 24
Finished	Feb 04 12:49:13 PM PST 24
Peak memory	200956 kb
Host	smart-a261ef20-5195-4a29-83db-bb7f1dd8e0bd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3046596235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.3046596235
Directory	/workspace/34.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.usbdev_intr_test.2471780608
Short name	T195
Test name
Test status
Simulation time	118083780 ps
CPU time	0.72 seconds
Started	Feb 04 12:49:06 PM PST 24
Finished	Feb 04 12:49:13 PM PST 24
Peak memory	201072 kb
Host	smart-3fb8a790-b31e-4737-bfa2-3f7c92fcb319
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2471780608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.2471780608
Directory	/workspace/37.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.usbdev_intr_test.1836988203
Short name	T220
Test name
Test status
Simulation time	25707826 ps
CPU time	0.61 seconds
Started	Feb 04 12:49:03 PM PST 24
Finished	Feb 04 12:49:09 PM PST 24
Peak memory	200936 kb
Host	smart-38e07517-80c1-41de-8c97-087c5d8c5f3a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1836988203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.1836988203
Directory	/workspace/39.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3859353383
Short name	T69
Test name
Test status
Simulation time	124946844 ps
CPU time	3.22 seconds
Started	Feb 04 12:48:15 PM PST 24
Finished	Feb 04 12:48:20 PM PST 24
Peak memory	201876 kb
Host	smart-fd984853-418d-43d1-93b7-687242c3ea4c
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859353383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.3859353383
Directory	/workspace/4.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.167236364
Short name	T30
Test name
Test status
Simulation time	35666572 ps
CPU time	0.72 seconds
Started	Feb 04 12:48:15 PM PST 24
Finished	Feb 04 12:48:18 PM PST 24
Peak memory	201736 kb
Host	smart-f8497546-dccc-448e-a7ed-dcc412e2a4f2
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167236364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.167236364
Directory	/workspace/4.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.782698147
Short name	T177
Test name
Test status
Simulation time	49076676 ps
CPU time	1.92 seconds
Started	Feb 04 12:48:09 PM PST 24
Finished	Feb 04 12:48:12 PM PST 24
Peak memory	210268 kb
Host	smart-d1937594-5378-41fa-abb2-5c0823ee49bd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782698147 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_mem_rw_with_rand_reset.782698147
Directory	/workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1306833557
Short name	T68
Test name
Test status
Simulation time	77683441 ps
CPU time	0.98 seconds
Started	Feb 04 12:48:34 PM PST 24
Finished	Feb 04 12:48:39 PM PST 24
Peak memory	201940 kb
Host	smart-5cae642e-148f-454e-a433-39e0b7171d03
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306833557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.1306833557
Directory	/workspace/4.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_intr_test.587185919
Short name	T93
Test name
Test status
Simulation time	84354333 ps
CPU time	0.69 seconds
Started	Feb 04 12:48:11 PM PST 24
Finished	Feb 04 12:48:12 PM PST 24
Peak memory	200848 kb
Host	smart-ea1227f8-1cc3-43d5-baaa-0cff72cf9c45
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=587185919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.587185919
Directory	/workspace/4.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1517731825
Short name	T227
Test name
Test status
Simulation time	71248584 ps
CPU time	2.16 seconds
Started	Feb 04 12:48:15 PM PST 24
Finished	Feb 04 12:48:19 PM PST 24
Peak memory	201936 kb
Host	smart-afa42330-b9cd-464d-90e3-12634556dcd3
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1517731825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.1517731825
Directory	/workspace/4.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3668975446
Short name	T175
Test name
Test status
Simulation time	50950932 ps
CPU time	1.34 seconds
Started	Feb 04 12:48:12 PM PST 24
Finished	Feb 04 12:48:14 PM PST 24
Peak memory	202096 kb
Host	smart-541eb2c3-957f-4f96-8212-99e1d7fbc111
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668975446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_c sr_outstanding.3668975446
Directory	/workspace/4.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/41.usbdev_intr_test.858101492
Short name	T181
Test name
Test status
Simulation time	22460672 ps
CPU time	0.63 seconds
Started	Feb 04 12:49:03 PM PST 24
Finished	Feb 04 12:49:08 PM PST 24
Peak memory	201016 kb
Host	smart-7bbc56a1-fedf-426e-808e-c9db8eea9a2f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=858101492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.858101492
Directory	/workspace/41.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.usbdev_intr_test.2413537482
Short name	T92
Test name
Test status
Simulation time	34893000 ps
CPU time	0.7 seconds
Started	Feb 04 12:49:03 PM PST 24
Finished	Feb 04 12:49:08 PM PST 24
Peak memory	200992 kb
Host	smart-3bcdc2ec-6572-47f0-9254-f8b8f73269d0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2413537482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.2413537482
Directory	/workspace/42.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.usbdev_intr_test.2513972277
Short name	T101
Test name
Test status
Simulation time	61638976 ps
CPU time	0.67 seconds
Started	Feb 04 12:49:12 PM PST 24
Finished	Feb 04 12:49:16 PM PST 24
Peak memory	201052 kb
Host	smart-d2a49c09-e016-4015-b446-726fb126ce3b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2513972277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.2513972277
Directory	/workspace/45.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.usbdev_intr_test.3857710179
Short name	T180
Test name
Test status
Simulation time	90683041 ps
CPU time	0.78 seconds
Started	Feb 04 12:49:03 PM PST 24
Finished	Feb 04 12:49:08 PM PST 24
Peak memory	200972 kb
Host	smart-b07ebad7-fac2-4f6a-b7da-44b73b99f04a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3857710179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.3857710179
Directory	/workspace/46.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.usbdev_intr_test.3594097587
Short name	T40
Test name
Test status
Simulation time	33387520 ps
CPU time	0.66 seconds
Started	Feb 04 12:49:16 PM PST 24
Finished	Feb 04 12:49:19 PM PST 24
Peak memory	200964 kb
Host	smart-ebce1560-707f-4b17-97a3-47682004d90a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3594097587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.3594097587
Directory	/workspace/47.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.usbdev_intr_test.339443408
Short name	T193
Test name
Test status
Simulation time	23692814 ps
CPU time	0.65 seconds
Started	Feb 04 12:49:04 PM PST 24
Finished	Feb 04 12:49:09 PM PST 24
Peak memory	200992 kb
Host	smart-7a3a9557-80a1-46f2-872b-8c0df066eb06
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=339443408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.339443408
Directory	/workspace/48.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.usbdev_intr_test.286256672
Short name	T174
Test name
Test status
Simulation time	34298157 ps
CPU time	0.68 seconds
Started	Feb 04 12:49:17 PM PST 24
Finished	Feb 04 12:49:19 PM PST 24
Peak memory	200884 kb
Host	smart-b9875aa5-6abf-492b-9ee3-5ee5f6ad4378
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=286256672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.286256672
Directory	/workspace/49.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.292463257
Short name	T202
Test name
Test status
Simulation time	85347283 ps
CPU time	1.93 seconds
Started	Feb 04 12:48:10 PM PST 24
Finished	Feb 04 12:48:13 PM PST 24
Peak memory	210276 kb
Host	smart-884fc408-c789-45d0-960b-e2cb6a5cbb8a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292463257 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_mem_rw_with_rand_reset.292463257
Directory	/workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3148703636
Short name	T33
Test name
Test status
Simulation time	121736183 ps
CPU time	1.09 seconds
Started	Feb 04 12:48:11 PM PST 24
Finished	Feb 04 12:48:13 PM PST 24
Peak memory	202008 kb
Host	smart-c519f750-9262-4e68-941f-509e0f4bdd31
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148703636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.3148703636
Directory	/workspace/5.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_intr_test.1879206358
Short name	T85
Test name
Test status
Simulation time	34394047 ps
CPU time	0.64 seconds
Started	Feb 04 12:48:11 PM PST 24
Finished	Feb 04 12:48:13 PM PST 24
Peak memory	201024 kb
Host	smart-07d17307-eb7d-4f21-8184-5c70081f1a4e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1879206358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.1879206358
Directory	/workspace/5.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2191295492
Short name	T56
Test name
Test status
Simulation time	68570687 ps
CPU time	0.99 seconds
Started	Feb 04 12:48:22 PM PST 24
Finished	Feb 04 12:48:25 PM PST 24
Peak memory	201892 kb
Host	smart-d5f011aa-9fa3-43e9-abf3-34a49965bb9a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191295492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_c sr_outstanding.2191295492
Directory	/workspace/5.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3936039163
Short name	T18
Test name
Test status
Simulation time	165323589 ps
CPU time	2.26 seconds
Started	Feb 04 12:48:16 PM PST 24
Finished	Feb 04 12:48:20 PM PST 24
Peak memory	201940 kb
Host	smart-d68080aa-c8aa-489c-bfb0-dd3922850aa5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3936039163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.3936039163
Directory	/workspace/5.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.569424558
Short name	T90
Test name
Test status
Simulation time	145654762 ps
CPU time	2.42 seconds
Started	Feb 04 12:48:31 PM PST 24
Finished	Feb 04 12:48:39 PM PST 24
Peak memory	202056 kb
Host	smart-60717225-fc76-4cf2-a9e8-4c7789727786
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=569424558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.569424558
Directory	/workspace/5.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3001594880
Short name	T170
Test name
Test status
Simulation time	60478311 ps
CPU time	2.19 seconds
Started	Feb 04 12:48:19 PM PST 24
Finished	Feb 04 12:48:24 PM PST 24
Peak memory	210232 kb
Host	smart-79a50d2c-8084-4f10-88b0-a483ea7dfea0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001594880 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_mem_rw_with_rand_reset.3001594880
Directory	/workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3053602491
Short name	T165
Test name
Test status
Simulation time	65159171 ps
CPU time	1 seconds
Started	Feb 04 12:48:13 PM PST 24
Finished	Feb 04 12:48:15 PM PST 24
Peak memory	202000 kb
Host	smart-26a59193-0833-4b33-962d-c68a6228f195
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053602491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.3053602491
Directory	/workspace/6.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_intr_test.2031682809
Short name	T216
Test name
Test status
Simulation time	20362951 ps
CPU time	0.6 seconds
Started	Feb 04 12:48:14 PM PST 24
Finished	Feb 04 12:48:16 PM PST 24
Peak memory	200964 kb
Host	smart-c4321f00-88af-489d-b478-3aa7b29ae789
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2031682809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.2031682809
Directory	/workspace/6.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3866878503
Short name	T82
Test name
Test status
Simulation time	149852673 ps
CPU time	1.36 seconds
Started	Feb 04 12:48:18 PM PST 24
Finished	Feb 04 12:48:22 PM PST 24
Peak memory	201908 kb
Host	smart-4dbf7ab0-3098-4939-8650-86de622366a2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866878503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_c sr_outstanding.3866878503
Directory	/workspace/6.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3649319042
Short name	T52
Test name
Test status
Simulation time	116491623 ps
CPU time	1.54 seconds
Started	Feb 04 12:48:15 PM PST 24
Finished	Feb 04 12:48:18 PM PST 24
Peak memory	201848 kb
Host	smart-1e991903-230a-4e86-9402-22e437a0058f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3649319042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.3649319042
Directory	/workspace/6.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2105625593
Short name	T183
Test name
Test status
Simulation time	52985614 ps
CPU time	1.84 seconds
Started	Feb 04 12:48:18 PM PST 24
Finished	Feb 04 12:48:22 PM PST 24
Peak memory	212168 kb
Host	smart-29f32fdd-cdab-4a18-b3d5-2610623096d4
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105625593 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_mem_rw_with_rand_reset.2105625593
Directory	/workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3498210930
Short name	T197
Test name
Test status
Simulation time	61681089 ps
CPU time	0.98 seconds
Started	Feb 04 12:48:24 PM PST 24
Finished	Feb 04 12:48:26 PM PST 24
Peak memory	202012 kb
Host	smart-9d6c052d-2e91-4dac-88bf-f6dedf156b5d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498210930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.3498210930
Directory	/workspace/7.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_intr_test.3341228712
Short name	T218
Test name
Test status
Simulation time	21488831 ps
CPU time	0.59 seconds
Started	Feb 04 12:48:18 PM PST 24
Finished	Feb 04 12:48:21 PM PST 24
Peak memory	200848 kb
Host	smart-d8361b02-6494-47a9-aed7-de50e81c3172
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3341228712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.3341228712
Directory	/workspace/7.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3050913136
Short name	T221
Test name
Test status
Simulation time	35622865 ps
CPU time	0.94 seconds
Started	Feb 04 12:48:15 PM PST 24
Finished	Feb 04 12:48:18 PM PST 24
Peak memory	201996 kb
Host	smart-f738f1bb-fa63-4dce-8dcb-96b248bc8784
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050913136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_c sr_outstanding.3050913136
Directory	/workspace/7.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.300720687
Short name	T190
Test name
Test status
Simulation time	260688622 ps
CPU time	2.67 seconds
Started	Feb 04 12:48:15 PM PST 24
Finished	Feb 04 12:48:19 PM PST 24
Peak memory	201964 kb
Host	smart-c1cbd1a4-0763-4144-9d7e-c3c75a387731
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=300720687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.300720687
Directory	/workspace/7.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2656899517
Short name	T230
Test name
Test status
Simulation time	56712588 ps
CPU time	1.43 seconds
Started	Feb 04 12:48:26 PM PST 24
Finished	Feb 04 12:48:29 PM PST 24
Peak memory	210136 kb
Host	smart-cf607e5f-b275-4ef8-84ce-ef232f1b9b0a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656899517 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_mem_rw_with_rand_reset.2656899517
Directory	/workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2673881801
Short name	T63
Test name
Test status
Simulation time	43152657 ps
CPU time	0.95 seconds
Started	Feb 04 12:48:33 PM PST 24
Finished	Feb 04 12:48:39 PM PST 24
Peak memory	202084 kb
Host	smart-7944f66d-e2a1-47dc-b7b5-d028961e28e9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673881801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.2673881801
Directory	/workspace/8.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3402823747
Short name	T186
Test name
Test status
Simulation time	41021797 ps
CPU time	0.98 seconds
Started	Feb 04 12:48:24 PM PST 24
Finished	Feb 04 12:48:26 PM PST 24
Peak memory	201940 kb
Host	smart-b2ebd0f4-aead-4742-ac7a-e9f590ee3bfe
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402823747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_c sr_outstanding.3402823747
Directory	/workspace/8.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.4022355659
Short name	T57
Test name
Test status
Simulation time	237904405 ps
CPU time	4.2 seconds
Started	Feb 04 12:48:14 PM PST 24
Finished	Feb 04 12:48:19 PM PST 24
Peak memory	201912 kb
Host	smart-a38e36c0-1f83-4fd5-807f-4346c06c37b4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=4022355659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.4022355659
Directory	/workspace/8.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.557824744
Short name	T16
Test name
Test status
Simulation time	35365594 ps
CPU time	1 seconds
Started	Feb 04 12:48:18 PM PST 24
Finished	Feb 04 12:48:21 PM PST 24
Peak memory	201936 kb
Host	smart-c7ac82a1-16e1-4294-a36a-fa9dc3907208
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557824744 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_mem_rw_with_rand_reset.557824744
Directory	/workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.4132804562
Short name	T34
Test name
Test status
Simulation time	58997588 ps
CPU time	0.96 seconds
Started	Feb 04 12:48:20 PM PST 24
Finished	Feb 04 12:48:23 PM PST 24
Peak memory	202060 kb
Host	smart-72502d23-fc86-4845-a43e-faee703c865c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132804562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.4132804562
Directory	/workspace/9.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2440091181
Short name	T211
Test name
Test status
Simulation time	77852929 ps
CPU time	1.05 seconds
Started	Feb 04 12:48:33 PM PST 24
Finished	Feb 04 12:48:39 PM PST 24
Peak memory	201996 kb
Host	smart-19d9460a-5531-4bce-ad88-cd48fc7368ec
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440091181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_c sr_outstanding.2440091181
Directory	/workspace/9.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2994587918
Short name	T214
Test name
Test status
Simulation time	86387513 ps
CPU time	2.47 seconds
Started	Feb 04 12:48:17 PM PST 24
Finished	Feb 04 12:48:21 PM PST 24
Peak memory	201828 kb
Host	smart-ce488a80-8fd5-446d-87ec-32983011c2f1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2994587918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.2994587918
Directory	/workspace/9.usbdev_tl_errors/latest

Test location	/workspace/coverage/default/0.usbdev_pkt_received.443236104
Short name	T72
Test name
Test status
Simulation time	8372884763 ps
CPU time	7.76 seconds
Started	Feb 04 12:49:51 PM PST 24
Finished	Feb 04 12:50:00 PM PST 24
Peak memory	201968 kb
Host	smart-78570956-abda-431f-b304-6def26f5c6ff
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44323 6104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.443236104
Directory	/workspace/0.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/0.usbdev_smoke.3120157539
Short name	T107
Test name
Test status
Simulation time	8369385054 ps
CPU time	7.37 seconds
Started	Feb 04 12:49:41 PM PST 24
Finished	Feb 04 12:49:52 PM PST 24
Peak memory	201912 kb
Host	smart-3706b63d-cef3-42ea-8541-66a9d0d0a41e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31201 57539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.3120157539
Directory	/workspace/0.usbdev_smoke/latest

Test location	/workspace/coverage/default/1.usbdev_smoke.984876338
Short name	T147
Test name
Test status
Simulation time	8376180353 ps
CPU time	7.08 seconds
Started	Feb 04 12:49:58 PM PST 24
Finished	Feb 04 12:50:14 PM PST 24
Peak memory	201844 kb
Host	smart-c081e1d0-3cc7-49c9-b3a0-349a30e2a5a2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98487 6338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.984876338
Directory	/workspace/1.usbdev_smoke/latest

Test location	/workspace/coverage/default/10.usbdev_smoke.2174778978
Short name	T159
Test name
Test status
Simulation time	8397319981 ps
CPU time	9.01 seconds
Started	Feb 04 12:50:03 PM PST 24
Finished	Feb 04 12:50:21 PM PST 24
Peak memory	201888 kb
Host	smart-50b14c98-7868-4637-a238-2e014211a1f8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21747 78978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.2174778978
Directory	/workspace/10.usbdev_smoke/latest

Test location	/workspace/coverage/default/11.usbdev_pkt_received.3930742420
Short name	T130
Test name
Test status
Simulation time	8426815367 ps
CPU time	7 seconds
Started	Feb 04 12:49:58 PM PST 24
Finished	Feb 04 12:50:13 PM PST 24
Peak memory	201940 kb
Host	smart-c59a88f3-5ecd-49cf-9a26-6789494ca1f2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39307 42420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.3930742420
Directory	/workspace/11.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/11.usbdev_smoke.4235494287
Short name	T148
Test name
Test status
Simulation time	8377814722 ps
CPU time	7.86 seconds
Started	Feb 04 12:49:56 PM PST 24
Finished	Feb 04 12:50:07 PM PST 24
Peak memory	201584 kb
Host	smart-7329dc97-347a-455a-b5a7-0cf7b29d8b6a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42354 94287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.4235494287
Directory	/workspace/11.usbdev_smoke/latest

Test location	/workspace/coverage/default/12.usbdev_smoke.2369162148
Short name	T140
Test name
Test status
Simulation time	8404528196 ps
CPU time	7.03 seconds
Started	Feb 04 12:49:56 PM PST 24
Finished	Feb 04 12:50:07 PM PST 24
Peak memory	201764 kb
Host	smart-b7303ca9-eb78-40a5-bbd0-3a525b1e4808
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23691 62148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.2369162148
Directory	/workspace/12.usbdev_smoke/latest

Test location	/workspace/coverage/default/13.usbdev_smoke.2928194425
Short name	T163
Test name
Test status
Simulation time	8372451887 ps
CPU time	7.79 seconds
Started	Feb 04 12:49:55 PM PST 24
Finished	Feb 04 12:50:07 PM PST 24
Peak memory	201816 kb
Host	smart-45dabea1-af62-48c5-a533-995cd3c6dc2c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29281 94425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.2928194425
Directory	/workspace/13.usbdev_smoke/latest

Test location	/workspace/coverage/default/14.usbdev_smoke.1138356700
Short name	T43
Test name
Test status
Simulation time	8364971438 ps
CPU time	8.89 seconds
Started	Feb 04 12:49:59 PM PST 24
Finished	Feb 04 12:50:18 PM PST 24
Peak memory	201936 kb
Host	smart-0b67cfda-777e-480b-8727-afc06a9999a8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11383 56700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.1138356700
Directory	/workspace/14.usbdev_smoke/latest

Test location	/workspace/coverage/default/15.usbdev_pkt_received.2447008353
Short name	T113
Test name
Test status
Simulation time	8409529876 ps
CPU time	8.34 seconds
Started	Feb 04 12:49:59 PM PST 24
Finished	Feb 04 12:50:18 PM PST 24
Peak memory	201848 kb
Host	smart-b5796d76-609b-4e2e-b3f1-5cdbafe5963d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24470 08353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.2447008353
Directory	/workspace/15.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/15.usbdev_smoke.58329900
Short name	T117
Test name
Test status
Simulation time	8372052114 ps
CPU time	7.57 seconds
Started	Feb 04 12:49:55 PM PST 24
Finished	Feb 04 12:50:07 PM PST 24
Peak memory	201836 kb
Host	smart-5cef21ad-bb3d-4b52-9c65-b62e15f2461f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58329 900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.58329900
Directory	/workspace/15.usbdev_smoke/latest

Test location	/workspace/coverage/default/16.usbdev_pkt_received.3253510501
Short name	T76
Test name
Test status
Simulation time	8391751255 ps
CPU time	9.43 seconds
Started	Feb 04 12:49:50 PM PST 24
Finished	Feb 04 12:50:00 PM PST 24
Peak memory	201848 kb
Host	smart-d974b837-b40f-400f-8bfa-3480f08fe521
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32535 10501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.3253510501
Directory	/workspace/16.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/16.usbdev_smoke.3775910323
Short name	T133
Test name
Test status
Simulation time	8370063633 ps
CPU time	7.81 seconds
Started	Feb 04 12:49:59 PM PST 24
Finished	Feb 04 12:50:16 PM PST 24
Peak memory	201844 kb
Host	smart-4e195dcd-5f13-4db8-9e38-818ecb9256dd
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37759 10323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.3775910323
Directory	/workspace/16.usbdev_smoke/latest

Test location	/workspace/coverage/default/18.usbdev_pkt_received.400153544
Short name	T150
Test name
Test status
Simulation time	8370847398 ps
CPU time	7.61 seconds
Started	Feb 04 12:50:00 PM PST 24
Finished	Feb 04 12:50:18 PM PST 24
Peak memory	201860 kb
Host	smart-32cdfb9b-2379-41e6-986c-7748cf5f105c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40015 3544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.400153544
Directory	/workspace/18.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/18.usbdev_smoke.1072444783
Short name	T139
Test name
Test status
Simulation time	8371359740 ps
CPU time	7.53 seconds
Started	Feb 04 12:49:57 PM PST 24
Finished	Feb 04 12:50:08 PM PST 24
Peak memory	202032 kb
Host	smart-ac073af7-84d8-4d9e-9692-bd19ec9a76df
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10724 44783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.1072444783
Directory	/workspace/18.usbdev_smoke/latest

Test location	/workspace/coverage/default/19.usbdev_smoke.690503586
Short name	T135
Test name
Test status
Simulation time	8368488549 ps
CPU time	6.96 seconds
Started	Feb 04 12:49:50 PM PST 24
Finished	Feb 04 12:49:58 PM PST 24
Peak memory	201948 kb
Host	smart-f457d51e-e6d0-4726-8fcb-47368dc2d936
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69050 3586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.690503586
Directory	/workspace/19.usbdev_smoke/latest

Test location	/workspace/coverage/default/2.usbdev_pkt_received.80068186
Short name	T132
Test name
Test status
Simulation time	8393888864 ps
CPU time	7.59 seconds
Started	Feb 04 12:49:56 PM PST 24
Finished	Feb 04 12:50:07 PM PST 24
Peak memory	202068 kb
Host	smart-f70451fb-98d1-43c9-a3cf-6dba53ce9ae2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80068 186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.80068186
Directory	/workspace/2.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/2.usbdev_sec_cm.3030584017
Short name	T7
Test name
Test status
Simulation time	96623112 ps
CPU time	0.91 seconds
Started	Feb 04 12:49:59 PM PST 24
Finished	Feb 04 12:50:10 PM PST 24
Peak memory	220220 kb
Host	smart-cbc56e7d-a5e8-488f-8038-75bf6b07d371
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3030584017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.3030584017
Directory	/workspace/2.usbdev_sec_cm/latest

Test location	/workspace/coverage/default/2.usbdev_smoke.225047387
Short name	T8
Test name
Test status
Simulation time	8370840235 ps
CPU time	7.62 seconds
Started	Feb 04 12:49:51 PM PST 24
Finished	Feb 04 12:50:01 PM PST 24
Peak memory	201852 kb
Host	smart-d4671828-ad34-4ca3-826f-91a44c2b30ae
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22504 7387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.225047387
Directory	/workspace/2.usbdev_smoke/latest

Test location	/workspace/coverage/default/20.usbdev_pkt_received.2741935488
Short name	T151
Test name
Test status
Simulation time	8380485897 ps
CPU time	7.7 seconds
Started	Feb 04 12:49:53 PM PST 24
Finished	Feb 04 12:50:03 PM PST 24
Peak memory	201976 kb
Host	smart-7845cf79-b2b1-443c-a503-171fcc0c1913
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27419 35488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.2741935488
Directory	/workspace/20.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/20.usbdev_smoke.3488775771
Short name	T110
Test name
Test status
Simulation time	8368593096 ps
CPU time	7.47 seconds
Started	Feb 04 12:49:48 PM PST 24
Finished	Feb 04 12:49:57 PM PST 24
Peak memory	201944 kb
Host	smart-df00d38f-98dd-4e71-9c77-5aa5ecb61154
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34887 75771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.3488775771
Directory	/workspace/20.usbdev_smoke/latest

Test location	/workspace/coverage/default/21.usbdev_pkt_received.3875270829
Short name	T137
Test name
Test status
Simulation time	8420193756 ps
CPU time	7.16 seconds
Started	Feb 04 12:49:58 PM PST 24
Finished	Feb 04 12:50:12 PM PST 24
Peak memory	201848 kb
Host	smart-477cabcf-7cf0-47dd-99ec-384c982a67e5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38752 70829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.3875270829
Directory	/workspace/21.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/21.usbdev_smoke.713527618
Short name	T149
Test name
Test status
Simulation time	8372131736 ps
CPU time	8.39 seconds
Started	Feb 04 12:49:51 PM PST 24
Finished	Feb 04 12:50:01 PM PST 24
Peak memory	201988 kb
Host	smart-531f1061-c3be-4c7e-8c7e-0207fcd5b20e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71352 7618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.713527618
Directory	/workspace/21.usbdev_smoke/latest

Test location	/workspace/coverage/default/22.usbdev_pkt_received.373496706
Short name	T106
Test name
Test status
Simulation time	8481368351 ps
CPU time	7.81 seconds
Started	Feb 04 12:49:53 PM PST 24
Finished	Feb 04 12:50:03 PM PST 24
Peak memory	201908 kb
Host	smart-81a3b3b9-7f38-47ba-b6d1-fed798a8c4c1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37349 6706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.373496706
Directory	/workspace/22.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/22.usbdev_smoke.586142098
Short name	T10
Test name
Test status
Simulation time	8367499033 ps
CPU time	7.71 seconds
Started	Feb 04 12:49:56 PM PST 24
Finished	Feb 04 12:50:08 PM PST 24
Peak memory	201872 kb
Host	smart-38669cb0-b903-40da-a42d-2cddcf322040
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58614 2098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.586142098
Directory	/workspace/22.usbdev_smoke/latest

Test location	/workspace/coverage/default/23.usbdev_pkt_received.1946363048
Short name	T128
Test name
Test status
Simulation time	8381609339 ps
CPU time	8.01 seconds
Started	Feb 04 12:49:59 PM PST 24
Finished	Feb 04 12:50:15 PM PST 24
Peak memory	201964 kb
Host	smart-43c1d6eb-c972-4661-aa7f-7ef6b41a2caf
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19463 63048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.1946363048
Directory	/workspace/23.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/23.usbdev_smoke.656886495
Short name	T41
Test name
Test status
Simulation time	8385412937 ps
CPU time	6.95 seconds
Started	Feb 04 12:49:58 PM PST 24
Finished	Feb 04 12:50:14 PM PST 24
Peak memory	201852 kb
Host	smart-c1847291-fd8f-4c9c-b7bb-8f527eec0dab
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65688 6495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.656886495
Directory	/workspace/23.usbdev_smoke/latest

Test location	/workspace/coverage/default/24.usbdev_pkt_received.3047253106
Short name	T145
Test name
Test status
Simulation time	8401476123 ps
CPU time	7.27 seconds
Started	Feb 04 12:49:57 PM PST 24
Finished	Feb 04 12:50:08 PM PST 24
Peak memory	201976 kb
Host	smart-0a457e2f-5058-483d-b967-ea1ffff15fa1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30472 53106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.3047253106
Directory	/workspace/24.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/24.usbdev_smoke.1155866777
Short name	T144
Test name
Test status
Simulation time	8369084116 ps
CPU time	7.74 seconds
Started	Feb 04 12:49:55 PM PST 24
Finished	Feb 04 12:50:07 PM PST 24
Peak memory	201940 kb
Host	smart-b5b38d15-f1de-4bef-8679-a6154de41de3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11558 66777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.1155866777
Directory	/workspace/24.usbdev_smoke/latest

Test location	/workspace/coverage/default/25.usbdev_pkt_received.818166685
Short name	T157
Test name
Test status
Simulation time	8424815464 ps
CPU time	7.31 seconds
Started	Feb 04 12:49:56 PM PST 24
Finished	Feb 04 12:50:08 PM PST 24
Peak memory	201920 kb
Host	smart-d2edc78e-5284-4bda-b51a-4ac251b19b2a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81816 6685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.818166685
Directory	/workspace/25.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/25.usbdev_smoke.2899415423
Short name	T141
Test name
Test status
Simulation time	8366124383 ps
CPU time	7.32 seconds
Started	Feb 04 12:49:57 PM PST 24
Finished	Feb 04 12:50:08 PM PST 24
Peak memory	201924 kb
Host	smart-2353c1bd-6413-493a-9eb5-b34af8269a0d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28994 15423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.2899415423
Directory	/workspace/25.usbdev_smoke/latest

Test location	/workspace/coverage/default/26.usbdev_pkt_received.3787174184
Short name	T156
Test name
Test status
Simulation time	8386703184 ps
CPU time	7.91 seconds
Started	Feb 04 12:49:58 PM PST 24
Finished	Feb 04 12:50:15 PM PST 24
Peak memory	201972 kb
Host	smart-b84a1e12-22cd-49b7-85d3-a0048d20d107
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37871 74184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.3787174184
Directory	/workspace/26.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/26.usbdev_smoke.1671169039
Short name	T164
Test name
Test status
Simulation time	8370640966 ps
CPU time	7.28 seconds
Started	Feb 04 12:49:53 PM PST 24
Finished	Feb 04 12:50:02 PM PST 24
Peak memory	201952 kb
Host	smart-c2ec98f3-2485-48b0-b038-e12b375c4aae
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16711 69039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.1671169039
Directory	/workspace/26.usbdev_smoke/latest

Test location	/workspace/coverage/default/28.usbdev_pkt_received.3908569154
Short name	T75
Test name
Test status
Simulation time	8385661408 ps
CPU time	7.36 seconds
Started	Feb 04 12:49:58 PM PST 24
Finished	Feb 04 12:50:15 PM PST 24
Peak memory	201856 kb
Host	smart-4e615cda-faf6-498e-a914-3cb7ab6c5714
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39085 69154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.3908569154
Directory	/workspace/28.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/28.usbdev_smoke.3493564772
Short name	T146
Test name
Test status
Simulation time	8366376067 ps
CPU time	7.05 seconds
Started	Feb 04 12:49:57 PM PST 24
Finished	Feb 04 12:50:08 PM PST 24
Peak memory	201984 kb
Host	smart-54bba5e4-dfd3-4e72-b871-83fe5a1988c3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34935 64772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.3493564772
Directory	/workspace/28.usbdev_smoke/latest

Test location	/workspace/coverage/default/29.usbdev_pkt_received.1422278968
Short name	T12
Test name
Test status
Simulation time	8388150591 ps
CPU time	7.31 seconds
Started	Feb 04 12:49:55 PM PST 24
Finished	Feb 04 12:50:06 PM PST 24
Peak memory	201836 kb
Host	smart-9b98c354-c031-40ac-81a5-e61a9fa8ac6c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14222 78968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.1422278968
Directory	/workspace/29.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/29.usbdev_smoke.3072224194
Short name	T74
Test name
Test status
Simulation time	8365860097 ps
CPU time	7.2 seconds
Started	Feb 04 12:49:59 PM PST 24
Finished	Feb 04 12:50:18 PM PST 24
Peak memory	201776 kb
Host	smart-4ba59ac1-8ced-47f6-97f6-0b682da86aba
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30722 24194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.3072224194
Directory	/workspace/29.usbdev_smoke/latest

Test location	/workspace/coverage/default/3.usbdev_pkt_received.1723183186
Short name	T46
Test name
Test status
Simulation time	8447682966 ps
CPU time	7 seconds
Started	Feb 04 12:49:59 PM PST 24
Finished	Feb 04 12:50:16 PM PST 24
Peak memory	201772 kb
Host	smart-e792d18b-88bf-475b-881c-ae48fdb71c32
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17231 83186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.1723183186
Directory	/workspace/3.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/3.usbdev_sec_cm.1483108042
Short name	T28
Test name
Test status
Simulation time	110975821 ps
CPU time	0.99 seconds
Started	Feb 04 12:49:42 PM PST 24
Finished	Feb 04 12:49:45 PM PST 24
Peak memory	220320 kb
Host	smart-74a65a84-8c4e-4b32-aaa4-c3fd7469c73f
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1483108042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.1483108042
Directory	/workspace/3.usbdev_sec_cm/latest

Test location	/workspace/coverage/default/3.usbdev_smoke.1151479982
Short name	T4
Test name
Test status
Simulation time	8367448180 ps
CPU time	7.15 seconds
Started	Feb 04 12:49:55 PM PST 24
Finished	Feb 04 12:50:06 PM PST 24
Peak memory	202048 kb
Host	smart-bb215567-8fb5-4bbb-a91d-095d897f43be
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11514 79982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.1151479982
Directory	/workspace/3.usbdev_smoke/latest

Test location	/workspace/coverage/default/30.usbdev_pkt_received.2150482664
Short name	T155
Test name
Test status
Simulation time	8400255775 ps
CPU time	7.29 seconds
Started	Feb 04 12:49:59 PM PST 24
Finished	Feb 04 12:50:17 PM PST 24
Peak memory	201244 kb
Host	smart-c674b9ba-a653-487e-b3f7-80dd07a15927
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21504 82664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.2150482664
Directory	/workspace/30.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/30.usbdev_smoke.4070727819
Short name	T162
Test name
Test status
Simulation time	8377526658 ps
CPU time	9.07 seconds
Started	Feb 04 12:50:01 PM PST 24
Finished	Feb 04 12:50:21 PM PST 24
Peak memory	201752 kb
Host	smart-f15a26bb-a0e5-40cb-b04a-f2b118e1522f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40707 27819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.4070727819
Directory	/workspace/30.usbdev_smoke/latest

Test location	/workspace/coverage/default/31.usbdev_pkt_received.1884483231
Short name	T108
Test name
Test status
Simulation time	8390778735 ps
CPU time	8.77 seconds
Started	Feb 04 12:49:55 PM PST 24
Finished	Feb 04 12:50:08 PM PST 24
Peak memory	201944 kb
Host	smart-382fe392-41ad-4e06-a58c-3994020bf7f8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18844 83231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.1884483231
Directory	/workspace/31.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/31.usbdev_smoke.2092280755
Short name	T154
Test name
Test status
Simulation time	8371683780 ps
CPU time	7.25 seconds
Started	Feb 04 12:49:59 PM PST 24
Finished	Feb 04 12:50:17 PM PST 24
Peak memory	201932 kb
Host	smart-998676b1-b28a-4b43-9263-23c91daec11e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20922 80755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.2092280755
Directory	/workspace/31.usbdev_smoke/latest

Test location	/workspace/coverage/default/32.usbdev_pkt_received.1234668572
Short name	T138
Test name
Test status
Simulation time	8415271410 ps
CPU time	7.11 seconds
Started	Feb 04 12:50:04 PM PST 24
Finished	Feb 04 12:50:19 PM PST 24
Peak memory	201988 kb
Host	smart-ef25ab61-a730-4fcd-bb70-05781fd12750
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12346 68572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.1234668572
Directory	/workspace/32.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/32.usbdev_smoke.2837412185
Short name	T136
Test name
Test status
Simulation time	8375791112 ps
CPU time	7.26 seconds
Started	Feb 04 12:49:59 PM PST 24
Finished	Feb 04 12:50:17 PM PST 24
Peak memory	201692 kb
Host	smart-7b9e01cd-7040-4aae-8446-2fff7720a119
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28374 12185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.2837412185
Directory	/workspace/32.usbdev_smoke/latest

Test location	/workspace/coverage/default/33.usbdev_pkt_received.3550176399
Short name	T120
Test name
Test status
Simulation time	8366371500 ps
CPU time	7.96 seconds
Started	Feb 04 12:50:04 PM PST 24
Finished	Feb 04 12:50:20 PM PST 24
Peak memory	201860 kb
Host	smart-9206b0a7-e6d6-43d1-bc4f-374e6b213811
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35501 76399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.3550176399
Directory	/workspace/33.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/33.usbdev_smoke.1288079620
Short name	T122
Test name
Test status
Simulation time	8383168602 ps
CPU time	7.07 seconds
Started	Feb 04 12:50:04 PM PST 24
Finished	Feb 04 12:50:19 PM PST 24
Peak memory	201932 kb
Host	smart-12d55640-7384-4ca7-b546-9799de1bed1f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12880 79620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.1288079620
Directory	/workspace/33.usbdev_smoke/latest

Test location	/workspace/coverage/default/34.usbdev_smoke.2728403456
Short name	T119
Test name
Test status
Simulation time	8369539127 ps
CPU time	7 seconds
Started	Feb 04 12:50:08 PM PST 24
Finished	Feb 04 12:50:21 PM PST 24
Peak memory	201908 kb
Host	smart-09abca3e-7b6f-48d1-b4c0-9512a78d481d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27284 03456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.2728403456
Directory	/workspace/34.usbdev_smoke/latest

Test location	/workspace/coverage/default/35.usbdev_pkt_received.3983184260
Short name	T126
Test name
Test status
Simulation time	8403479536 ps
CPU time	8.53 seconds
Started	Feb 04 12:50:05 PM PST 24
Finished	Feb 04 12:50:21 PM PST 24
Peak memory	201952 kb
Host	smart-e6b9124a-bb51-4a4a-bd1e-196663bc5a1c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39831 84260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.3983184260
Directory	/workspace/35.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/35.usbdev_smoke.2508633247
Short name	T160
Test name
Test status
Simulation time	8379555532 ps
CPU time	8.12 seconds
Started	Feb 04 12:50:05 PM PST 24
Finished	Feb 04 12:50:20 PM PST 24
Peak memory	201856 kb
Host	smart-b944912b-15f2-48c0-aecc-ed1ca5efc499
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25086 33247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.2508633247
Directory	/workspace/35.usbdev_smoke/latest

Test location	/workspace/coverage/default/36.usbdev_pkt_received.2957750765
Short name	T49
Test name
Test status
Simulation time	8384161172 ps
CPU time	7.7 seconds
Started	Feb 04 12:50:02 PM PST 24
Finished	Feb 04 12:50:20 PM PST 24
Peak memory	201848 kb
Host	smart-5ecf5cd7-cb75-4c53-a1a0-e8081ed7de47
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29577 50765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.2957750765
Directory	/workspace/36.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/36.usbdev_smoke.2071729794
Short name	T1
Test name
Test status
Simulation time	8380454165 ps
CPU time	7.12 seconds
Started	Feb 04 12:50:10 PM PST 24
Finished	Feb 04 12:50:22 PM PST 24
Peak memory	201844 kb
Host	smart-ffb52c7c-92f1-49db-9e07-cb0bec3682a3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20717 29794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.2071729794
Directory	/workspace/36.usbdev_smoke/latest

Test location	/workspace/coverage/default/37.usbdev_pkt_received.2340580182
Short name	T109
Test name
Test status
Simulation time	8404919214 ps
CPU time	8.16 seconds
Started	Feb 04 12:50:09 PM PST 24
Finished	Feb 04 12:50:22 PM PST 24
Peak memory	201848 kb
Host	smart-39e92995-e3f3-45c3-9330-31b292b93d9b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23405 80182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.2340580182
Directory	/workspace/37.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/37.usbdev_smoke.909903860
Short name	T143
Test name
Test status
Simulation time	8381629976 ps
CPU time	7.37 seconds
Started	Feb 04 12:50:10 PM PST 24
Finished	Feb 04 12:50:23 PM PST 24
Peak memory	201884 kb
Host	smart-666c797d-8077-4c6e-af18-323ac601e9a3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90990 3860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.909903860
Directory	/workspace/37.usbdev_smoke/latest

Test location	/workspace/coverage/default/38.usbdev_pkt_received.2360063117
Short name	T115
Test name
Test status
Simulation time	8381554451 ps
CPU time	7.35 seconds
Started	Feb 04 12:50:09 PM PST 24
Finished	Feb 04 12:50:21 PM PST 24
Peak memory	201912 kb
Host	smart-f188a8c8-2280-4c66-a380-84f4c6edb4de
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23600 63117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.2360063117
Directory	/workspace/38.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/38.usbdev_smoke.1879177841
Short name	T134
Test name
Test status
Simulation time	8368592184 ps
CPU time	9.79 seconds
Started	Feb 04 12:50:13 PM PST 24
Finished	Feb 04 12:50:27 PM PST 24
Peak memory	201908 kb
Host	smart-be510ce1-5ea1-4c76-aecc-b322e79bbc1e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18791 77841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.1879177841
Directory	/workspace/38.usbdev_smoke/latest

Test location	/workspace/coverage/default/39.usbdev_pkt_received.2782378116
Short name	T5
Test name
Test status
Simulation time	8398421931 ps
CPU time	7.08 seconds
Started	Feb 04 12:50:08 PM PST 24
Finished	Feb 04 12:50:21 PM PST 24
Peak memory	201912 kb
Host	smart-79578836-d29c-4dae-b158-ec4519da87a8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27823 78116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.2782378116
Directory	/workspace/39.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/39.usbdev_smoke.3056100850
Short name	T116
Test name
Test status
Simulation time	8380200792 ps
CPU time	7.18 seconds
Started	Feb 04 12:50:09 PM PST 24
Finished	Feb 04 12:50:21 PM PST 24
Peak memory	201936 kb
Host	smart-88f8a49b-4e1a-4d18-b8e3-c3e715a8797b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30561 00850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.3056100850
Directory	/workspace/39.usbdev_smoke/latest

Test location	/workspace/coverage/default/4.usbdev_smoke.3611094401
Short name	T158
Test name
Test status
Simulation time	8377087097 ps
CPU time	7.92 seconds
Started	Feb 04 12:49:40 PM PST 24
Finished	Feb 04 12:49:50 PM PST 24
Peak memory	201928 kb
Host	smart-02696da9-4051-4d9e-8f33-c94256092c1d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36110 94401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.3611094401
Directory	/workspace/4.usbdev_smoke/latest

Test location	/workspace/coverage/default/40.usbdev_smoke.2828994637
Short name	T127
Test name
Test status
Simulation time	8368849976 ps
CPU time	7.11 seconds
Started	Feb 04 12:50:04 PM PST 24
Finished	Feb 04 12:50:19 PM PST 24
Peak memory	201856 kb
Host	smart-8d021230-57b6-427f-8327-d6feeb7ee15e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28289 94637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.2828994637
Directory	/workspace/40.usbdev_smoke/latest

Test location	/workspace/coverage/default/42.usbdev_pkt_received.2077070990
Short name	T112
Test name
Test status
Simulation time	8367124498 ps
CPU time	9.3 seconds
Started	Feb 04 12:50:05 PM PST 24
Finished	Feb 04 12:50:21 PM PST 24
Peak memory	201872 kb
Host	smart-1dada12a-3fd5-42c6-864d-c60c4c31421f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20770 70990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.2077070990
Directory	/workspace/42.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/42.usbdev_smoke.1067476750
Short name	T73
Test name
Test status
Simulation time	8373809972 ps
CPU time	7.02 seconds
Started	Feb 04 12:50:09 PM PST 24
Finished	Feb 04 12:50:21 PM PST 24
Peak memory	201936 kb
Host	smart-be235412-f17d-43d1-81d8-03dbf030d746
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10674 76750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.1067476750
Directory	/workspace/42.usbdev_smoke/latest

Test location	/workspace/coverage/default/43.usbdev_pkt_received.329822106
Short name	T142
Test name
Test status
Simulation time	8400208216 ps
CPU time	8.5 seconds
Started	Feb 04 12:50:09 PM PST 24
Finished	Feb 04 12:50:23 PM PST 24
Peak memory	201960 kb
Host	smart-aa53e05d-132d-4d5d-a87f-b637655ebbfb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32982 2106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.329822106
Directory	/workspace/43.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/43.usbdev_smoke.3906791617
Short name	T114
Test name
Test status
Simulation time	8378077096 ps
CPU time	7.54 seconds
Started	Feb 04 12:50:16 PM PST 24
Finished	Feb 04 12:50:26 PM PST 24
Peak memory	201972 kb
Host	smart-1187886b-539b-4469-b3a7-802e2d5cd545
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39067 91617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.3906791617
Directory	/workspace/43.usbdev_smoke/latest

Test location	/workspace/coverage/default/44.usbdev_pkt_received.4260518058
Short name	T121
Test name
Test status
Simulation time	8380750782 ps
CPU time	7.12 seconds
Started	Feb 04 12:50:08 PM PST 24
Finished	Feb 04 12:50:21 PM PST 24
Peak memory	201840 kb
Host	smart-71744141-ed8b-45fd-af69-4eebbb7aa00a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42605 18058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.4260518058
Directory	/workspace/44.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/44.usbdev_smoke.927748158
Short name	T9
Test name
Test status
Simulation time	8364862695 ps
CPU time	7.84 seconds
Started	Feb 04 12:50:14 PM PST 24
Finished	Feb 04 12:50:26 PM PST 24
Peak memory	201972 kb
Host	smart-c1fd0bf6-2a3b-43f0-8ce6-a6ac167e1fb8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92774 8158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.927748158
Directory	/workspace/44.usbdev_smoke/latest

Test location	/workspace/coverage/default/45.usbdev_pkt_received.1734891392
Short name	T118
Test name
Test status
Simulation time	8406641041 ps
CPU time	7.61 seconds
Started	Feb 04 12:50:16 PM PST 24
Finished	Feb 04 12:50:26 PM PST 24
Peak memory	201976 kb
Host	smart-edf80227-ee5c-4e48-b5e7-68ebfdb07673
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17348 91392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.1734891392
Directory	/workspace/45.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/45.usbdev_smoke.1508771471
Short name	T123
Test name
Test status
Simulation time	8381212350 ps
CPU time	7.02 seconds
Started	Feb 04 12:50:13 PM PST 24
Finished	Feb 04 12:50:24 PM PST 24
Peak memory	201848 kb
Host	smart-b809057a-ab13-418b-bae9-d2fad345837c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15087 71471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.1508771471
Directory	/workspace/45.usbdev_smoke/latest

Test location	/workspace/coverage/default/46.usbdev_smoke.2181947867
Short name	T125
Test name
Test status
Simulation time	8366613876 ps
CPU time	7.95 seconds
Started	Feb 04 12:50:09 PM PST 24
Finished	Feb 04 12:50:22 PM PST 24
Peak memory	201908 kb
Host	smart-cfc6ccbb-c290-40cd-bfcd-0d25f5e9d132
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21819 47867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.2181947867
Directory	/workspace/46.usbdev_smoke/latest

Test location	/workspace/coverage/default/47.usbdev_smoke.3826334518
Short name	T42
Test name
Test status
Simulation time	8373858180 ps
CPU time	6.93 seconds
Started	Feb 04 12:50:10 PM PST 24
Finished	Feb 04 12:50:23 PM PST 24
Peak memory	201948 kb
Host	smart-cf36ff3a-dae0-4139-9114-33cff179d0fa
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38263 34518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.3826334518
Directory	/workspace/47.usbdev_smoke/latest

Test location	/workspace/coverage/default/48.usbdev_pkt_received.2773548913
Short name	T44
Test name
Test status
Simulation time	8407273540 ps
CPU time	7.82 seconds
Started	Feb 04 12:50:12 PM PST 24
Finished	Feb 04 12:50:25 PM PST 24
Peak memory	201852 kb
Host	smart-68997e49-715f-4a54-b947-54df4d4cac40
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27735 48913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.2773548913
Directory	/workspace/48.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/48.usbdev_smoke.2385098628
Short name	T11
Test name
Test status
Simulation time	8370285319 ps
CPU time	8.75 seconds
Started	Feb 04 12:50:16 PM PST 24
Finished	Feb 04 12:50:28 PM PST 24
Peak memory	201968 kb
Host	smart-680bc8f2-c02a-4eca-99eb-592ae9690e93
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23850 98628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.2385098628
Directory	/workspace/48.usbdev_smoke/latest

Test location	/workspace/coverage/default/49.usbdev_pkt_received.3658470347
Short name	T161
Test name
Test status
Simulation time	8402692076 ps
CPU time	7.38 seconds
Started	Feb 04 12:50:16 PM PST 24
Finished	Feb 04 12:50:27 PM PST 24
Peak memory	201988 kb
Host	smart-c2c98f4c-e263-40c5-b0ab-7ccbe50e3266
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36584 70347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.3658470347
Directory	/workspace/49.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/49.usbdev_smoke.1769493355
Short name	T131
Test name
Test status
Simulation time	8370270351 ps
CPU time	7.08 seconds
Started	Feb 04 12:50:12 PM PST 24
Finished	Feb 04 12:50:24 PM PST 24
Peak memory	201888 kb
Host	smart-0f56589e-b675-4c14-996c-50a78bded389
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17694 93355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.1769493355
Directory	/workspace/49.usbdev_smoke/latest

Test location	/workspace/coverage/default/5.usbdev_pkt_received.1786668662
Short name	T111
Test name
Test status
Simulation time	8405213361 ps
CPU time	8.91 seconds
Started	Feb 04 12:49:39 PM PST 24
Finished	Feb 04 12:49:51 PM PST 24
Peak memory	201868 kb
Host	smart-40caf5dc-1320-4117-bfef-c715c180ef56
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17866 68662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.1786668662
Directory	/workspace/5.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/5.usbdev_smoke.2672983379
Short name	T71
Test name
Test status
Simulation time	8369154858 ps
CPU time	7.89 seconds
Started	Feb 04 12:49:38 PM PST 24
Finished	Feb 04 12:49:50 PM PST 24
Peak memory	201972 kb
Host	smart-0c3d6089-f9a3-4bb3-9214-83d8f2bb78e3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26729 83379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.2672983379
Directory	/workspace/5.usbdev_smoke/latest

Test location	/workspace/coverage/default/6.usbdev_smoke.1958521904
Short name	T129
Test name
Test status
Simulation time	8371806717 ps
CPU time	8.39 seconds
Started	Feb 04 12:50:00 PM PST 24
Finished	Feb 04 12:50:19 PM PST 24
Peak memory	201888 kb
Host	smart-1403722b-129a-41f5-a320-19d1b49ff246
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19585 21904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.1958521904
Directory	/workspace/6.usbdev_smoke/latest

Test location	/workspace/coverage/default/7.usbdev_pkt_received.63817604
Short name	T152
Test name
Test status
Simulation time	8378652633 ps
CPU time	7.45 seconds
Started	Feb 04 12:49:57 PM PST 24
Finished	Feb 04 12:50:08 PM PST 24
Peak memory	201760 kb
Host	smart-9e69d746-a533-4da7-96d4-81ee3f428388
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63817 604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.63817604
Directory	/workspace/7.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/7.usbdev_smoke.4082796611
Short name	T2
Test name
Test status
Simulation time	8374543566 ps
CPU time	7.82 seconds
Started	Feb 04 12:49:55 PM PST 24
Finished	Feb 04 12:50:07 PM PST 24
Peak memory	202040 kb
Host	smart-a82490f9-f09c-49d8-9b4a-571415757702
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40827 96611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.4082796611
Directory	/workspace/7.usbdev_smoke/latest

Test location	/workspace/coverage/default/8.usbdev_pkt_received.1225649354
Short name	T153
Test name
Test status
Simulation time	8394904261 ps
CPU time	7.03 seconds
Started	Feb 04 12:50:00 PM PST 24
Finished	Feb 04 12:50:18 PM PST 24
Peak memory	201884 kb
Host	smart-ae598e33-a735-489e-961d-0fa3f61deb6a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12256 49354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.1225649354
Directory	/workspace/8.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/8.usbdev_smoke.988433634
Short name	T77
Test name
Test status
Simulation time	8375401312 ps
CPU time	7.94 seconds
Started	Feb 04 12:49:59 PM PST 24
Finished	Feb 04 12:50:17 PM PST 24
Peak memory	201928 kb
Host	smart-bca2fd30-4020-4629-aaf8-019529cfbcad
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98843 3634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.988433634
Directory	/workspace/8.usbdev_smoke/latest

Test location	/workspace/coverage/default/9.usbdev_pkt_received.2395273663
Short name	T3
Test name
Test status
Simulation time	8406230762 ps
CPU time	7.14 seconds
Started	Feb 04 12:49:57 PM PST 24
Finished	Feb 04 12:50:08 PM PST 24
Peak memory	202032 kb
Host	smart-334a65b6-f7f7-426a-b3af-874165be64dc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23952 73663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.2395273663
Directory	/workspace/9.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/9.usbdev_smoke.2150121398
Short name	T124
Test name
Test status
Simulation time	8370558519 ps
CPU time	7.04 seconds
Started	Feb 04 12:50:01 PM PST 24
Finished	Feb 04 12:50:19 PM PST 24
Peak memory	201888 kb
Host	smart-12fd6dfe-3a30-470d-94b6-08d69d989151
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21501 21398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.2150121398
Directory	/workspace/9.usbdev_smoke/latest