Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	68	0	68	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	17	0	17	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	68	0	68	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	483	1		T1	2		T2	2		T3	3
all_pins[1]	483	1		T1	2		T2	2		T3	3
all_pins[2]	483	1		T1	2		T2	2		T3	3
all_pins[3]	483	1		T1	2		T2	2		T3	3
all_pins[4]	483	1		T1	2		T2	2		T3	3
all_pins[5]	483	1		T1	2		T2	2		T3	3
all_pins[6]	483	1		T1	2		T2	2		T3	3
all_pins[7]	483	1		T1	2		T2	2		T3	3
all_pins[8]	483	1		T1	2		T2	2		T3	3
all_pins[9]	483	1		T1	2		T2	2		T3	3
all_pins[10]	483	1		T1	2		T2	2		T3	3
all_pins[11]	483	1		T1	2		T2	2		T3	3
all_pins[12]	483	1		T1	2		T2	2		T3	3
all_pins[13]	483	1		T1	2		T2	2		T3	3
all_pins[14]	483	1		T1	2		T2	2		T3	3
all_pins[15]	483	1		T1	2		T2	2		T3	3
all_pins[16]	483	1		T1	2		T2	2		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	7332	1		T1	33		T2	33		T3	49
values[0x1]	879	1		T1	1		T2	1		T3	2
transitions[0x0=>0x1]	668	1		T1	1		T2	1		T3	2
transitions[0x1=>0x0]	673	1		T1	1		T2	1		T3	2

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	68	0	68	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	322	1		T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	161	1		T1	1		T2	1		T3	2
all_pins[0]	transitions[0x0=>0x1]	146	1		T1	1		T2	1		T3	2
all_pins[0]	transitions[0x1=>0x0]	32	1		T36	1		T24	3		T40	3
all_pins[1]	values[0x0]	436	1		T1	2		T2	2		T3	3
all_pins[1]	values[0x1]	47	1		T35	1		T36	1		T24	3
all_pins[1]	transitions[0x0=>0x1]	30	1		T35	1		T36	1		T24	2
all_pins[1]	transitions[0x1=>0x0]	31	1		T36	2		T39	2		T40	1
all_pins[2]	values[0x0]	435	1		T1	2		T2	2		T3	3
all_pins[2]	values[0x1]	48	1		T36	2		T24	1		T39	2
all_pins[2]	transitions[0x0=>0x1]	35	1		T36	2		T24	1		T39	2
all_pins[2]	transitions[0x1=>0x0]	41	1		T35	1		T36	3		T24	2
all_pins[3]	values[0x0]	429	1		T1	2		T2	2		T3	3
all_pins[3]	values[0x1]	54	1		T35	1		T36	3		T24	2
all_pins[3]	transitions[0x0=>0x1]	36	1		T35	1		T36	3		T95	1
all_pins[3]	transitions[0x1=>0x0]	35	1		T24	2		T39	3		T40	2
all_pins[4]	values[0x0]	430	1		T1	2		T2	2		T3	3
all_pins[4]	values[0x1]	53	1		T24	4		T39	3		T40	2
all_pins[4]	transitions[0x0=>0x1]	38	1		T24	4		T39	3		T95	2
all_pins[4]	transitions[0x1=>0x0]	30	1		T36	4		T24	1		T95	1
all_pins[5]	values[0x0]	438	1		T1	2		T2	2		T3	3
all_pins[5]	values[0x1]	45	1		T36	4		T24	1		T40	2
all_pins[5]	transitions[0x0=>0x1]	38	1		T36	4		T95	1		T85	2
all_pins[5]	transitions[0x1=>0x0]	31	1		T35	2		T24	2		T39	1
all_pins[6]	values[0x0]	445	1		T1	2		T2	2		T3	3
all_pins[6]	values[0x1]	38	1		T35	2		T24	3		T39	1
all_pins[6]	transitions[0x0=>0x1]	23	1		T35	2		T24	3		T39	1
all_pins[6]	transitions[0x1=>0x0]	32	1		T24	1		T39	3		T40	1
all_pins[7]	values[0x0]	436	1		T1	2		T2	2		T3	3
all_pins[7]	values[0x1]	47	1		T24	1		T39	3		T40	2
all_pins[7]	transitions[0x0=>0x1]	38	1		T24	1		T40	2		T95	1
all_pins[7]	transitions[0x1=>0x0]	29	1		T35	2		T36	1		T24	2
all_pins[8]	values[0x0]	445	1		T1	2		T2	2		T3	3
all_pins[8]	values[0x1]	38	1		T35	2		T36	1		T24	2
all_pins[8]	transitions[0x0=>0x1]	33	1		T35	1		T36	1		T24	2
all_pins[8]	transitions[0x1=>0x0]	30	1		T35	1		T36	1		T24	4
all_pins[9]	values[0x0]	448	1		T1	2		T2	2		T3	3
all_pins[9]	values[0x1]	35	1		T35	2		T36	1		T24	4
all_pins[9]	transitions[0x0=>0x1]	23	1		T35	2		T36	1		T24	1
all_pins[9]	transitions[0x1=>0x0]	31	1		T35	1		T36	1		T95	2
all_pins[10]	values[0x0]	440	1		T1	2		T2	2		T3	3
all_pins[10]	values[0x1]	43	1		T35	1		T36	1		T24	3
all_pins[10]	transitions[0x0=>0x1]	31	1		T35	1		T36	1		T24	3
all_pins[10]	transitions[0x1=>0x0]	33	1		T35	1		T36	1		T24	2
all_pins[11]	values[0x0]	438	1		T1	2		T2	2		T3	3
all_pins[11]	values[0x1]	45	1		T35	1		T36	1		T24	2
all_pins[11]	transitions[0x0=>0x1]	35	1		T35	1		T36	1		T85	2
all_pins[11]	transitions[0x1=>0x0]	36	1		T35	1		T36	4		T24	4
all_pins[12]	values[0x0]	437	1		T1	2		T2	2		T3	3
all_pins[12]	values[0x1]	46	1		T35	1		T36	4		T24	6
all_pins[12]	transitions[0x0=>0x1]	35	1		T35	1		T36	4		T24	5
all_pins[12]	transitions[0x1=>0x0]	29	1		T35	2		T39	1		T95	1
all_pins[13]	values[0x0]	443	1		T1	2		T2	2		T3	3
all_pins[13]	values[0x1]	40	1		T35	2		T24	1		T39	2
all_pins[13]	transitions[0x0=>0x1]	33	1		T35	2		T24	1		T39	1
all_pins[13]	transitions[0x1=>0x0]	40	1		T35	1		T36	2		T24	1
all_pins[14]	values[0x0]	436	1		T1	2		T2	2		T3	3
all_pins[14]	values[0x1]	47	1		T35	1		T36	2		T24	1
all_pins[14]	transitions[0x0=>0x1]	30	1		T35	1		T36	2		T24	1
all_pins[14]	transitions[0x1=>0x0]	38	1		T35	1		T24	3		T40	3
all_pins[15]	values[0x0]	428	1		T1	2		T2	2		T3	3
all_pins[15]	values[0x1]	55	1		T35	1		T24	3		T39	2
all_pins[15]	transitions[0x0=>0x1]	43	1		T35	1		T24	3		T39	2
all_pins[15]	transitions[0x1=>0x0]	25	1		T35	1		T36	2		T40	1
all_pins[16]	values[0x0]	446	1		T1	2		T2	2		T3	3
all_pins[16]	values[0x1]	37	1		T35	1		T36	2		T40	2
all_pins[16]	transitions[0x0=>0x1]	21	1		T36	2		T40	1		T95	2
all_pins[16]	transitions[0x1=>0x0]	150	1		T1	1		T2	1		T3	2