Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	23	0	23	100.00
Crosses	102	0	102	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	17	0	17	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	102	0	102	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	203	1		T35	7		T36	7		T24	7
all_values[1]	203	1		T35	7		T36	7		T24	7
all_values[2]	203	1		T35	7		T36	7		T24	7
all_values[3]	203	1		T35	7		T36	7		T24	7
all_values[4]	203	1		T35	7		T36	7		T24	7
all_values[5]	203	1		T35	7		T36	7		T24	7
all_values[6]	203	1		T35	7		T36	7		T24	7
all_values[7]	203	1		T35	7		T36	7		T24	7
all_values[8]	203	1		T35	7		T36	7		T24	7
all_values[9]	203	1		T35	7		T36	7		T24	7
all_values[10]	203	1		T35	7		T36	7		T24	7
all_values[11]	203	1		T35	7		T36	7		T24	7
all_values[12]	203	1		T35	7		T36	7		T24	7
all_values[13]	203	1		T35	7		T36	7		T24	7
all_values[14]	203	1		T35	7		T36	7		T24	7
all_values[15]	203	1		T35	7		T36	7		T24	7
all_values[16]	203	1		T35	7		T36	7		T24	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1862	1		T35	79		T36	66		T24	57
auto[1]	1589	1		T35	40		T36	53		T24	62

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	659	1		T35	13		T36	16		T24	17
auto[1]	2792	1		T35	106		T36	103		T24	102

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2040	1		T35	65		T36	74		T24	71
auto[1]	1411	1		T35	54		T36	45		T24	48

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	102	0	102	100.00
Automatically Generated Cross Bins	102	0	102	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	24	1		T35	1		T36	1		T40	3
all_values[0]	auto[0]	auto[0]	auto[1]	45	1		T24	3		T39	1		T40	2
all_values[0]	auto[0]	auto[1]	auto[0]	13	1		T95	2		T92	2		T99	1
all_values[0]	auto[0]	auto[1]	auto[1]	49	1		T35	4		T36	3		T24	1
all_values[0]	auto[1]	auto[0]	auto[1]	39	1		T36	1		T24	1		T39	4
all_values[0]	auto[1]	auto[1]	auto[1]	33	1		T35	2		T36	2		T24	2
all_values[1]	auto[0]	auto[0]	auto[0]	24	1		T36	1		T39	2		T92	1
all_values[1]	auto[0]	auto[0]	auto[1]	38	1		T35	1		T24	1		T39	1
all_values[1]	auto[0]	auto[1]	auto[0]	16	1		T36	1		T92	1		T93	1
all_values[1]	auto[0]	auto[1]	auto[1]	29	1		T36	2		T24	3		T40	1
all_values[1]	auto[1]	auto[0]	auto[1]	52	1		T35	4		T36	1		T24	2
all_values[1]	auto[1]	auto[1]	auto[1]	44	1		T35	2		T36	2		T24	1
all_values[2]	auto[0]	auto[0]	auto[0]	22	1		T24	1		T39	1		T40	1
all_values[2]	auto[0]	auto[0]	auto[1]	41	1		T35	2		T36	2		T24	1
all_values[2]	auto[0]	auto[1]	auto[0]	19	1		T24	1		T39	1		T40	2
all_values[2]	auto[0]	auto[1]	auto[1]	43	1		T35	1		T36	2		T24	2
all_values[2]	auto[1]	auto[0]	auto[1]	45	1		T35	3		T36	2		T24	2
all_values[2]	auto[1]	auto[1]	auto[1]	33	1		T35	1		T36	1		T39	1
all_values[3]	auto[0]	auto[0]	auto[0]	15	1		T35	1		T36	2		T24	1
all_values[3]	auto[0]	auto[0]	auto[1]	37	1		T35	2		T24	1		T39	3
all_values[3]	auto[0]	auto[1]	auto[0]	15	1		T40	3		T97	1		T100	2
all_values[3]	auto[0]	auto[1]	auto[1]	56	1		T35	2		T36	3		T24	1
all_values[3]	auto[1]	auto[0]	auto[1]	53	1		T35	2		T36	1		T24	3
all_values[3]	auto[1]	auto[1]	auto[1]	27	1		T36	1		T24	1		T85	2
all_values[4]	auto[0]	auto[0]	auto[0]	21	1		T35	1		T39	2		T40	1
all_values[4]	auto[0]	auto[0]	auto[1]	40	1		T35	2		T36	5		T24	2
all_values[4]	auto[0]	auto[1]	auto[0]	9	1		T97	5		T101	2		T102	2
all_values[4]	auto[0]	auto[1]	auto[1]	42	1		T35	2		T24	1		T39	2
all_values[4]	auto[1]	auto[0]	auto[1]	45	1		T35	2		T36	2		T24	3
all_values[4]	auto[1]	auto[1]	auto[1]	46	1		T24	1		T39	1		T40	2
all_values[5]	auto[0]	auto[0]	auto[0]	31	1		T35	2		T36	1		T24	1
all_values[5]	auto[0]	auto[0]	auto[1]	38	1		T35	3		T24	1		T95	1
all_values[5]	auto[0]	auto[1]	auto[0]	20	1		T36	1		T39	1		T40	1
all_values[5]	auto[0]	auto[1]	auto[1]	38	1		T36	1		T24	4		T40	1
all_values[5]	auto[1]	auto[0]	auto[1]	36	1		T35	2		T36	2		T95	2
all_values[5]	auto[1]	auto[1]	auto[1]	40	1		T36	2		T24	1		T40	1
all_values[6]	auto[0]	auto[0]	auto[0]	23	1		T36	1		T39	1		T95	1
all_values[6]	auto[0]	auto[0]	auto[1]	47	1		T35	2		T39	4		T40	1
all_values[6]	auto[0]	auto[1]	auto[0]	14	1		T36	1		T85	3		T92	2
all_values[6]	auto[0]	auto[1]	auto[1]	31	1		T35	1		T36	3		T24	3
all_values[6]	auto[1]	auto[0]	auto[1]	50	1		T35	3		T36	1		T24	2
all_values[6]	auto[1]	auto[1]	auto[1]	38	1		T35	1		T36	1		T24	2
all_values[7]	auto[0]	auto[0]	auto[0]	25	1		T35	2		T24	2		T93	2
all_values[7]	auto[0]	auto[0]	auto[1]	36	1		T36	2		T39	2		T40	3
all_values[7]	auto[0]	auto[1]	auto[0]	12	1		T24	2		T94	2		T97	1
all_values[7]	auto[0]	auto[1]	auto[1]	54	1		T35	4		T36	3		T24	2
all_values[7]	auto[1]	auto[0]	auto[1]	37	1		T35	1		T36	2		T39	2
all_values[7]	auto[1]	auto[1]	auto[1]	39	1		T24	1		T39	1		T40	3
all_values[8]	auto[0]	auto[0]	auto[0]	26	1		T36	1		T85	3		T92	3
all_values[8]	auto[0]	auto[0]	auto[1]	42	1		T36	1		T24	4		T40	1
all_values[8]	auto[0]	auto[1]	auto[0]	25	1		T92	2		T97	2		T100	3
all_values[8]	auto[0]	auto[1]	auto[1]	27	1		T35	3		T36	1		T39	2
all_values[8]	auto[1]	auto[0]	auto[1]	44	1		T35	3		T36	2		T24	1
all_values[8]	auto[1]	auto[1]	auto[1]	39	1		T35	1		T36	2		T24	2
all_values[9]	auto[0]	auto[0]	auto[0]	21	1		T24	2		T39	1		T40	1
all_values[9]	auto[0]	auto[0]	auto[1]	53	1		T35	2		T36	3		T39	3
all_values[9]	auto[0]	auto[1]	auto[0]	12	1		T24	1		T40	1		T97	1
all_values[9]	auto[0]	auto[1]	auto[1]	26	1		T24	1		T39	1		T40	1
all_values[9]	auto[1]	auto[0]	auto[1]	50	1		T35	3		T36	3		T39	1
all_values[9]	auto[1]	auto[1]	auto[1]	41	1		T35	2		T36	1		T24	3
all_values[10]	auto[0]	auto[0]	auto[0]	39	1		T35	2		T36	2		T40	5
all_values[10]	auto[0]	auto[0]	auto[1]	39	1		T35	2		T36	2		T24	1
all_values[10]	auto[0]	auto[1]	auto[0]	14	1		T40	2		T93	1		T96	1
all_values[10]	auto[0]	auto[1]	auto[1]	40	1		T36	2		T24	4		T39	2
all_values[10]	auto[1]	auto[0]	auto[1]	44	1		T35	3		T24	2		T39	1
all_values[10]	auto[1]	auto[1]	auto[1]	27	1		T36	1		T39	1		T85	1
all_values[11]	auto[0]	auto[0]	auto[0]	21	1		T35	1		T24	1		T39	2
all_values[11]	auto[0]	auto[0]	auto[1]	41	1		T35	2		T36	6		T24	1
all_values[11]	auto[0]	auto[1]	auto[0]	18	1		T39	1		T40	2		T92	2
all_values[11]	auto[0]	auto[1]	auto[1]	35	1		T35	1		T24	2		T40	2
all_values[11]	auto[1]	auto[0]	auto[1]	50	1		T36	1		T24	1		T39	3
all_values[11]	auto[1]	auto[1]	auto[1]	38	1		T35	3		T24	2		T40	1
all_values[12]	auto[0]	auto[0]	auto[0]	23	1		T36	1		T39	1		T96	1
all_values[12]	auto[0]	auto[0]	auto[1]	39	1		T35	3		T39	1		T40	2
all_values[12]	auto[0]	auto[1]	auto[0]	11	1		T97	1		T100	1		T103	2
all_values[12]	auto[0]	auto[1]	auto[1]	49	1		T36	3		T24	2		T39	2
all_values[12]	auto[1]	auto[0]	auto[1]	41	1		T35	4		T36	1		T24	1
all_values[12]	auto[1]	auto[1]	auto[1]	40	1		T36	2		T24	4		T39	2
all_values[13]	auto[0]	auto[0]	auto[0]	22	1		T35	1		T36	2		T95	1
all_values[13]	auto[0]	auto[0]	auto[1]	36	1		T24	1		T39	1		T40	1
all_values[13]	auto[0]	auto[1]	auto[0]	19	1		T96	1		T97	1		T98	2
all_values[13]	auto[0]	auto[1]	auto[1]	46	1		T35	3		T36	4		T24	4
all_values[13]	auto[1]	auto[0]	auto[1]	48	1		T36	1		T24	1		T39	3
all_values[13]	auto[1]	auto[1]	auto[1]	32	1		T35	3		T24	1		T39	1
all_values[14]	auto[0]	auto[0]	auto[0]	17	1		T24	1		T95	1		T93	1
all_values[14]	auto[0]	auto[0]	auto[1]	43	1		T35	3		T36	2		T24	3
all_values[14]	auto[0]	auto[1]	auto[0]	13	1		T85	2		T94	1		T98	1
all_values[14]	auto[0]	auto[1]	auto[1]	49	1		T36	1		T39	2		T40	3
all_values[14]	auto[1]	auto[0]	auto[1]	49	1		T35	2		T36	3		T24	3
all_values[14]	auto[1]	auto[1]	auto[1]	32	1		T35	2		T36	1		T85	2
all_values[15]	auto[0]	auto[0]	auto[0]	9	1		T35	1		T39	1		T85	1
all_values[15]	auto[0]	auto[0]	auto[1]	31	1		T35	3		T36	2		T39	1
all_values[15]	auto[0]	auto[1]	auto[0]	12	1		T94	2		T97	1		T104	3
all_values[15]	auto[0]	auto[1]	auto[1]	50	1		T36	2		T24	4		T39	2
all_values[15]	auto[1]	auto[0]	auto[1]	56	1		T35	3		T36	2		T24	2
all_values[15]	auto[1]	auto[1]	auto[1]	45	1		T36	1		T24	1		T39	2
all_values[16]	auto[0]	auto[0]	auto[0]	35	1		T35	1		T36	1		T24	2
all_values[16]	auto[0]	auto[0]	auto[1]	37	1		T35	3		T36	1		T24	1
all_values[16]	auto[0]	auto[1]	auto[0]	19	1		T24	2		T85	2		T96	1
all_values[16]	auto[0]	auto[1]	auto[1]	34	1		T35	1		T36	2		T95	1
all_values[16]	auto[1]	auto[0]	auto[1]	42	1		T35	1		T36	2		T24	2
all_values[16]	auto[1]	auto[1]	auto[1]	36	1		T35	1		T36	1		T39	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal