Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.35	90.70	57.14	93.90		75.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	51341712	10504	0	0
ep_in_enable_rd_A	51341712	571	0	0
ep_out_enable_rd_A	51341712	687	0	0
in_iso_rd_A	51341712	688	0	0
intr_enable_rd_A	51341712	879	0	0
out_iso_rd_A	51341712	786	0	0
phy_config_rd_A	51341712	384	0	0
phy_pins_drive_rd_A	51341712	621	0	0
rxenable_setup_rd_A	51341712	779	0	0
set_nak_out_rd_A	51341712	584	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51341712	10504	0	0
T14	4272	346	0	0
T15	11449	6	0	0
T16	9745	671	0	0
T28	1384	0	0	0
T45	1892	0	0	0
T46	3140	0	0	0
T51	880	0	0	0
T52	2639	308	0	0
T53	0	619	0	0
T54	0	1076	0	0
T55	0	643	0	0
T56	0	857	0	0
T59	1307	0	0	0
T60	1455	0	0	0
T64	0	3	0	0
T73	0	10	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51341712	571	0	0
T22	2621	5	0	0
T48	3827	19	0	0
T49	1499	0	0	0
T50	1159	0	0	0
T53	9262	0	0	0
T56	0	6	0	0
T62	1822	0	0	0
T63	1186	0	0	0
T64	12075	0	0	0
T65	994	0	0	0
T72	2006	0	0	0
T75	0	51	0	0
T91	0	48	0	0
T92	0	89	0	0
T93	0	5	0	0
T94	0	5	0	0
T95	0	26	0	0
T96	0	4	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51341712	687	0	0
T22	2621	13	0	0
T48	3827	15	0	0
T49	1499	0	0	0
T50	1159	0	0	0
T53	9262	0	0	0
T62	1822	0	0	0
T63	1186	0	0	0
T64	12075	0	0	0
T65	994	0	0	0
T72	2006	0	0	0
T75	0	39	0	0
T91	0	64	0	0
T92	0	156	0	0
T94	0	2	0	0
T95	0	24	0	0
T96	0	5	0	0
T97	0	124	0	0
T98	0	2	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51341712	688	0	0
T22	2621	5	0	0
T48	3827	21	0	0
T49	1499	0	0	0
T50	1159	0	0	0
T53	9262	0	0	0
T56	0	1	0	0
T62	1822	0	0	0
T63	1186	0	0	0
T64	12075	0	0	0
T65	994	0	0	0
T72	2006	0	0	0
T75	0	14	0	0
T91	0	38	0	0
T92	0	112	0	0
T94	0	5	0	0
T95	0	40	0	0
T96	0	2	0	0
T97	0	159	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51341712	879	0	0
T22	2621	2	0	0
T45	1892	0	0	0
T46	3140	0	0	0
T47	2870	0	0	0
T48	3827	8	0	0
T49	1499	0	0	0
T51	880	0	0	0
T52	2639	0	0	0
T59	1307	17	0	0
T60	1455	0	0	0
T75	0	64	0	0
T91	0	21	0	0
T92	0	192	0	0
T94	0	10	0	0
T95	0	57	0	0
T99	0	18	0	0
T100	0	14	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51341712	786	0	0
T22	2621	11	0	0
T48	3827	17	0	0
T49	1499	0	0	0
T50	1159	0	0	0
T53	9262	0	0	0
T62	1822	0	0	0
T63	1186	0	0	0
T64	12075	0	0	0
T65	994	0	0	0
T72	2006	0	0	0
T75	0	91	0	0
T91	0	73	0	0
T92	0	207	0	0
T94	0	5	0	0
T95	0	6	0	0
T96	0	5	0	0
T97	0	50	0	0
T98	0	26	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51341712	384	0	0
T22	2621	7	0	0
T48	3827	13	0	0
T49	1499	0	0	0
T50	1159	0	0	0
T53	9262	0	0	0
T62	1822	0	0	0
T63	1186	0	0	0
T64	12075	0	0	0
T65	994	0	0	0
T72	2006	0	0	0
T75	0	30	0	0
T91	0	40	0	0
T92	0	71	0	0
T94	0	6	0	0
T95	0	1	0	0
T96	0	5	0	0
T97	0	23	0	0
T101	0	21	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51341712	621	0	0
T22	2621	7	0	0
T48	3827	22	0	0
T49	1499	0	0	0
T50	1159	0	0	0
T53	9262	0	0	0
T56	0	4	0	0
T62	1822	0	0	0
T63	1186	0	0	0
T64	12075	0	0	0
T65	994	0	0	0
T72	2006	0	0	0
T75	0	65	0	0
T91	0	68	0	0
T92	0	143	0	0
T94	0	5	0	0
T95	0	3	0	0
T96	0	1	0	0
T97	0	62	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51341712	779	0	0
T22	2621	14	0	0
T48	3827	23	0	0
T49	1499	0	0	0
T50	1159	0	0	0
T53	9262	0	0	0
T58	0	6	0	0
T62	1822	0	0	0
T63	1186	0	0	0
T64	12075	0	0	0
T65	994	0	0	0
T72	2006	0	0	0
T75	0	79	0	0
T91	0	83	0	0
T92	0	90	0	0
T94	0	2	0	0
T95	0	27	0	0
T96	0	2	0	0
T97	0	136	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51341712	584	0	0
T22	2621	11	0	0
T48	3827	6	0	0
T49	1499	0	0	0
T50	1159	0	0	0
T53	9262	0	0	0
T56	0	2	0	0
T62	1822	0	0	0
T63	1186	0	0	0
T64	12075	0	0	0
T65	994	0	0	0
T72	2006	0	0	0
T75	0	52	0	0
T91	0	19	0	0
T92	0	75	0	0
T94	0	3	0	0
T95	0	2	0	0
T96	0	6	0	0
T97	0	96	0	0