Unified Coverage Report :: Module :: usbdev

Module : usbdev

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.35	90.70	57.14	93.90		75.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	83.35	90.70	57.14	93.90		75.00	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.35	90.70	57.14	93.90		75.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.96	94.83	84.31	97.14	31.25	93.34	96.91

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_event	100.00	100.00				100.00
gen_no_stubbed_memory.u_memory_1p	98.96	95.83	100.00			100.00	100.00
gen_no_stubbed_memory.u_tlul2sram	83.77	85.71	70.94			78.41	100.00
i_usbdev_iomux	61.67	88.89	44.44			83.33	30.00
intr_av_empty	89.58	100.00	58.33			100.00	100.00
intr_av_overflow	81.25	100.00	25.00			100.00	100.00
intr_disconnected	89.58	100.00	58.33			100.00	100.00
intr_frame	81.25	100.00	25.00			100.00	100.00
intr_host_lost	81.25	100.00	25.00			100.00	100.00
intr_hw_pkt_received	93.75	100.00	75.00			100.00	100.00
intr_hw_pkt_sent	81.25	100.00	25.00			100.00	100.00
intr_link_in_err	81.25	100.00	25.00			100.00	100.00
intr_link_out_err	81.25	100.00	25.00			100.00	100.00
intr_link_reset	89.58	100.00	58.33			100.00	100.00
intr_link_resume	81.25	100.00	25.00			100.00	100.00
intr_link_suspend	81.25	100.00	25.00			100.00	100.00
intr_powered	89.58	100.00	58.33			100.00	100.00
intr_rx_bitstuff_err	81.25	100.00	25.00			100.00	100.00
intr_rx_crc_err	81.25	100.00	25.00			100.00	100.00
intr_rx_full	81.25	100.00	25.00			100.00	100.00
intr_rx_pid_err	81.25	100.00	25.00			100.00	100.00
tlul_assert_device	95.24	100.00				85.71	100.00
u_reg	95.45	98.09	93.71	100.00		98.34	87.10
usbdev_avfifo	82.08	95.00	58.33			75.00	100.00
usbdev_csr_assert	100.00						100.00
usbdev_impl	72.78	84.21	72.41		31.25	76.03	100.00
usbdev_rxfifo	83.58	95.00	61.54			77.78	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : usbdev

	Line No.	Total	Covered	Percent
TOTAL		129	117	90.70
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
ALWAYS	194	5	5	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	275	1	1	100.00
CONT_ASSIGN	276	1	1	100.00
CONT_ASSIGN	280	1	0	0.00
ALWAYS	303	0	0
ALWAYS	303	3	3	100.00
ALWAYS	311	0	0
ALWAYS	311	4	4	100.00
ALWAYS	320	0	0
ALWAYS	320	3	3	100.00
ALWAYS	327	0	0
ALWAYS	327	3	3	100.00
ALWAYS	334	0	0
ALWAYS	334	3	3	100.00
ALWAYS	341	0	0
ALWAYS	341	2	2	100.00
ALWAYS	347	3	3	100.00
ALWAYS	354	3	2	66.67
ALWAYS	361	0	0
ALWAYS	361	3	0	0.00
ALWAYS	370	3	3	100.00
ALWAYS	382	3	3	100.00
ALWAYS	389	0	0
ALWAYS	389	3	0	0.00
ALWAYS	396	10	9	90.00
ALWAYS	414	0	0
ALWAYS	414	3	3	100.00
ALWAYS	422	0	0
ALWAYS	422	3	3	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	433	1	1	100.00
CONT_ASSIGN	434	1	1	100.00
CONT_ASSIGN	533	1	1	100.00
CONT_ASSIGN	534	1	1	100.00
CONT_ASSIGN	536	1	1	100.00
CONT_ASSIGN	537	1	1	100.00
CONT_ASSIGN	555	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
ALWAYS	564	0	0
ALWAYS	564	8	8	100.00
CONT_ASSIGN	644	1	1	100.00
CONT_ASSIGN	645	1	1	100.00
CONT_ASSIGN	646	1	1	100.00
CONT_ASSIGN	647	1	1	100.00
CONT_ASSIGN	655	1	1	100.00
ALWAYS	664	8	7	87.50
CONT_ASSIGN	678	1	1	100.00
CONT_ASSIGN	679	0	0
CONT_ASSIGN	682	1	1	100.00
CONT_ASSIGN	683	1	1	100.00
CONT_ASSIGN	740	1	1	100.00
CONT_ASSIGN	741	1	1	100.00
CONT_ASSIGN	745	1	1	100.00
CONT_ASSIGN	995	1	1	100.00
CONT_ASSIGN	996	1	1	100.00
CONT_ASSIGN	997	1	1	100.00
CONT_ASSIGN	998	1	1	100.00
CONT_ASSIGN	1038	1	1	100.00
CONT_ASSIGN	1041	1	1	100.00
CONT_ASSIGN	1050	1	1	100.00
ALWAYS	1053	5	3	60.00
ALWAYS	1062	3	3	100.00
CONT_ASSIGN	1075	1	1	100.00
CONT_ASSIGN	1078	1	1	100.00
CONT_ASSIGN	1085	1	1	100.00
ALWAYS	1089	3	3	100.00
CONT_ASSIGN	1096	1	1	100.00
CONT_ASSIGN	1101	1	1	100.00
CONT_ASSIGN	1103	1	1	100.00
CONT_ASSIGN	1111	0	0
CONT_ASSIGN	1113	0	0
CONT_ASSIGN	1115	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
118	1	1
192	1	1
194	1	1
195	1	1
197	1	1
198	1	1
200	1	1
221	1	1
222	1	1
223	1	1
247	1	1
272	1	1
273	1	1
274	1	1
275	1	1
276	1	1
280	0	1
303	1	1
304	1	1
305	1	1
311	1	1
312	1	1
313	1	1
314	1	1
320	1	1
321	1	1
322	1	1
327	1	1
328	1	1
329	1	1
334	1	1
335	1	1
336	1	1
341	1	1
342	1	1
347	1	1
348	1	1
349	1	1
354	1	1
355	1	1
356	0	1
			MISSING_ELSE
361	0	1
362	0	1
363	0	1
370	1	1
371	1	1
372	1	1
382	1	1
383	1	1
384	1	1
			MISSING_ELSE
389	0	1
390	0	1
391	0	1
396	1	1
397	1	1
398	1	1
399	1	1
400	1	1
402	1	1
404	1	1
405	1	1
406	1	1
408	0	1
			MISSING_ELSE
414	1	1
415	1	1
416	1	1
422	1	1
423	1	1
424	1	1
432	1	1
433	1	1
434	1	1
533	1	1
534	1	1
536	1	1
537	1	1
555	1	1
558	1	1
564	1	1
565	1	1
566	1	1
567	1	1
568	1	1
569	1	1
571	1	1
572	1	1
644	1	1
645	1	1
646	1	1
647	1	1
655	1	1
664	1	1
665	1	1
666	1	1
667	1	1
669	1	1
670	1	1
672	1	1
673	0	1
			MISSING_ELSE
678	1	1
679		unreachable
682	1	1
683	1	1
740	1	1
741	1	1
745	1	1
995	1	1
996	1	1
997	1	1
998	1	1
1038	1	1
1041	1	1
1050	1	1
1053	1	1
1054	1	1
1055	0	1
1056	1	1
1057	0	1
			MISSING_ELSE
1062	1	1
1063	1	1
1065	1	1
1075	1	1
1078	1	1
1085	1	1
1089	1	1
1090	1	1
1092	1	1
1096	1	1
1101	1	1
1103	1	1
1111		unreachable
1113		unreachable
1115		unreachable

---

Cond Coverage for Module : usbdev

	Total	Covered	Percent
Conditions	84	48	57.14
Logical	84	48	57.14
Non-Logical	0	0
Event	0	0

 LINE       192
 EXPRESSION (ns_cnt == 6'd47)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       221
 EXPRESSION (connect_en & ((~av_rvalid)))
             -----1----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       222
 EXPRESSION (reg2hw.avbuffer.qe & ((~av_fifo_wready)))
             ---------1--------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       223
 EXPRESSION (connect_en & ((~rx_fifo_rvalid)))
             -----1----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       247
 EXPRESSION (reg2hw.rxfifo.ep.re | reg2hw.rxfifo.setup.re | reg2hw.rxfifo.size.re | reg2hw.rxfifo.buffer.re)
             ---------1---------   -----------2----------   ----------3----------   -----------4-----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Not Covered
1	0	0	0	Not Covered

 LINE       349
 EXPRESSION (reg2hw.data_toggle_clear[i].q & reg2hw.data_toggle_clear[i].qe)
             --------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       355
 EXPRESSION (in_ep_xact_end && in_endpoint_val)
             -------1------    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Not Covered

 LINE       383
 EXPRESSION (rx_wvalid && out_endpoint_val)
             ----1----    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       402
 EXPRESSION (setup_received & out_endpoint_val)
             -------1------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T4,T5,T6

 LINE       406
 EXPRESSION (in_ep_xact_end & in_endpoint_val)
             -------1------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Not Covered

 LINE       424
 EXPRESSION (reg2hw.configin[i].rdy.q | reg2hw.configin[i].pend.q)
             ------------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       433
 EXPRESSION (cfg_pinflip ? 1'b0 : usb_pullup_en)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       434
 EXPRESSION (((!cfg_pinflip)) ? 1'b0 : usb_pullup_en)
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       537
 EXPRESSION (reg2hw.usbctrl.resume_link_active.qe & reg2hw.usbctrl.resume_link_active.q)
             ------------------1-----------------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       644
 EXPRESSION (usb_mem_b_req | sw_mem_a_req)
             ------1------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       645
 EXPRESSION (usb_mem_b_req ? usb_mem_b_write : sw_mem_a_write)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       646
 EXPRESSION (usb_mem_b_req ? usb_mem_b_addr : sw_mem_a_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       647
 EXPRESSION (usb_mem_b_req ? usb_mem_b_wdata : sw_mem_a_wdata)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       670
 EXPRESSION (usb_mem_b_req & ((!usb_mem_b_write)))
             ------1------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       678
 EXPRESSION (gen_no_stubbed_memory.mem_rvalid & ((!gen_no_stubbed_memory.mem_rsteering)))
             ----------------1---------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       683
 EXPRESSION (gen_no_stubbed_memory.mem_b_read_q ? gen_no_stubbed_memory.mem_rdata : gen_no_stubbed_memory.mem_b_rdata_q)
             -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       745
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       1041
 EXPRESSION (use_diff_rcvr & ((~link_suspend)))
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       1050
 EXPRESSION (usb_rcvr_ok_counter_q == '0)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1054
 EXPRESSION (use_diff_rcvr & ((!usb_rx_enable_o)))
             ------1------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       1056
 EXPRESSION (us_tick && (usb_rcvr_ok_counter_q > '0))
             ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       1078
 EXPRESSION (usb_ref_disable ? 1'b0 : event_sof)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       1085
 EXPRESSION (usb_ref_pulse_o ? 1'b1 : ((((!link_active)) || host_lost || usb_ref_disable) ? 1'b0 : usb_ref_val_q))
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       1085
 SUB-EXPRESSION ((((!link_active)) || host_lost || usb_ref_disable) ? 1'b0 : usb_ref_val_q)
                 -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1085
 SUB-EXPRESSION (((!link_active)) || host_lost || usb_ref_disable)
                 --------1-------    ----2----    -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Covered	T1,T2,T3

 LINE       1101
 EXPRESSION (reg2hw.wake_control.suspend_req.qe & reg2hw.wake_control.suspend_req.q)
             -----------------1----------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       1103
 EXPRESSION (reg2hw.wake_control.wake_ack.qe & reg2hw.wake_control.wake_ack.q)
             ---------------1---------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Toggle Coverage for Module : usbdev

	Total	Covered	Percent
Totals	67	60	89.55
Total Bits	426	400	93.90
Total Bits 0->1	213	200	93.90
Total Bits 1->0	213	200	93.90

Ports	67	60	89.55
Port Bits	426	400	93.90
Port Bits 0->1	213	200	93.90
Port Bits 1->0	213	200	93.90

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_aon_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_aon_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T10	Yes	T2,T3,T10	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T2,T3,T7	Yes	T2,T3,T7	INPUT
tl_i.a_source[7:0]	Yes	Yes	T2,T3,T7	Yes	T2,T3,T7	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
cio_usb_dp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_usb_dn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
usb_rx_d_i	No	No		No		INPUT
cio_usb_dp_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cio_usb_dp_en_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cio_usb_dn_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cio_usb_dn_en_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
usb_tx_se0_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
usb_tx_d_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cio_sense_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
usb_dp_pullup_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
usb_dn_pullup_o	Yes	Yes	T20	Yes	T20	OUTPUT
usb_rx_enable_o	Yes	Yes	T21,T15,T22	Yes	T21,T15,T22	OUTPUT
usb_tx_use_d_se0_o	Yes	Yes	T21,T15,T22	Yes	T21,T15,T22	OUTPUT
usb_aon_suspend_req_o	Yes	Yes	T22,T23,T20	Yes	T22,T23,T20	OUTPUT
usb_aon_wake_ack_o	Yes	Yes	T21,T24,T15	Yes	T21,T24,T15	OUTPUT
usb_aon_bus_reset_i	Unreachable	Unreachable		Unreachable		INPUT
usb_aon_sense_lost_i	Unreachable	Unreachable		Unreachable		INPUT
usb_aon_wake_detect_active_i	Unreachable	Unreachable		Unreachable		INPUT
usb_ref_val_o	No	No		No		OUTPUT
usb_ref_pulse_o	No	No		No		OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
intr_pkt_received_o	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
intr_pkt_sent_o	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT
intr_powered_o	Yes	Yes	T21,T26,T15	Yes	T21,T24,T26	OUTPUT
intr_disconnected_o	Yes	Yes	T25,T21,T24	Yes	T25,T21,T24	OUTPUT
intr_host_lost_o	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT
intr_link_reset_o	Yes	Yes	T25,T27,T28	Yes	T25,T27,T28	OUTPUT
intr_link_suspend_o	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT
intr_link_resume_o	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT
intr_av_empty_o	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT
intr_rx_full_o	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT
intr_av_overflow_o	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT
intr_link_in_err_o	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT
intr_link_out_err_o	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT
intr_rx_crc_err_o	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT
intr_rx_pid_err_o	Yes	Yes	T25,T27,T28	Yes	T25,T27,T28	OUTPUT
intr_rx_bitstuff_err_o	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT
intr_frame_o	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : usbdev

	Line No.	Total	Covered	Percent
Branches		40	30	75.00
TERNARY	433	2	1	50.00
TERNARY	434	2	1	50.00
TERNARY	1078	2	1	50.00
TERNARY	1085	3	2	66.67
TERNARY	645	2	2	100.00
TERNARY	646	2	2	100.00
TERNARY	647	2	2	100.00
TERNARY	683	2	1	50.00
IF	194	3	3	100.00
IF	355	2	1	50.00
IF	383	2	2	100.00
IF	398	4	3	75.00
IF	567	2	2	100.00
IF	1054	3	1	33.33
IF	1062	2	2	100.00
IF	1089	2	2	100.00
IF	664	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	433	(cfg_pinflip) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	434	((!cfg_pinflip)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	1078	(usb_ref_disable) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1085	(usb_ref_pulse_o) ? 
-2-:	1085	((((!link_active) || host_lost) || usb_ref_disable)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	645	(usb_mem_b_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	646	(usb_mem_b_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	647	(usb_mem_b_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	683	(gen_no_stubbed_memory.mem_b_read_q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	194	if ((!rst_n))
-2-:	197	if (us_tick)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	if ((in_ep_xact_end && in_endpoint_val))

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	383	if ((rx_wvalid && out_endpoint_val))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	398	if (event_link_reset)
-2-:	402	if ((setup_received & out_endpoint_val))
-3-:	406	if ((in_ep_xact_end & in_endpoint_val))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T5,T6
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	567	if (((setup_received && out_endpoint_val) && (out_endpoint == 4'((unsigned'(i))))))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1054	if ((use_diff_rcvr & (!usb_rx_enable_o)))
-2-:	1056	if ((us_tick && (usb_rcvr_ok_counter_q > '0)))

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1062	if ((!rst_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1089	if ((!rst_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	664	if ((!rst_ni))
-2-:	672	if (gen_no_stubbed_memory.mem_b_read_q)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : usbdev

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	34	34	100.00	34	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	34	34	100.00	34	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertsKnown_A	50722704	50687057	0	0
CIODnEnKnown_A	50722704	50687057	0	0
CIODnKnown_A	50722704	50687057	0	0
CIODpEnKnown_A	50722704	50687057	0	0
CIODpKnown_A	50722704	50687057	0	0
FpvSecCmRegWeOnehotCheck_A	50722704	90	0	0
TlOAReadyKnown_A	50722704	50687057	0	0
TlODValidKnown_A	50722704	50687057	0	0
USBAonSuspendReqKnown_A	50722704	50687057	0	0
USBAonWakeAckKnown_A	50722704	50687057	0	0
USBDnPUKnown_A	50722704	50687057	0	0
USBDpPUKnown_A	50722704	50687057	0	0
USBIntrAvEmptyKnown_A	50722704	50687057	0	0
USBIntrAvOverKnown_A	50722704	50687057	0	0
USBIntrDisConKnown_A	50722704	50687057	0	0
USBIntrFrameKnown_A	50722704	50687057	0	0
USBIntrHostLostKnown_A	50722704	50687057	0	0
USBIntrLinkInErrKnown_A	50722704	50687057	0	0
USBIntrLinkOutErrKnown_A	50722704	50687057	0	0
USBIntrLinkResKnown_A	50722704	50687057	0	0
USBIntrLinkRstKnown_A	50722704	50687057	0	0
USBIntrLinkSusKnown_A	50722704	50687057	0	0
USBIntrPktRcvdKnown_A	50722704	50687057	0	0
USBIntrPktSentKnown_A	50722704	50687057	0	0
USBIntrPwrdKnown_A	50722704	50687057	0	0
USBIntrRxBitstuffErrKnown_A	50722704	50687057	0	0
USBIntrRxCrCErrKnown_A	50722704	50687057	0	0
USBIntrRxFullKnown_A	50722704	50687057	0	0
USBIntrRxPidErrKnown_A	50722704	50687057	0	0
USBRefPulseKnown_A	50722704	50687057	0	0
USBRefValKnown_A	50722704	50687057	0	0
USBRxEnableKnown_A	50722704	50687057	0	0
USBTxDKnown_A	50722704	50687057	0	0
USBTxSe0Known_A	50722704	50687057	0	0

AlertsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50687057	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

CIODnEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50687057	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

CIODnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50687057	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

CIODpEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50687057	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

CIODpKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50687057	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	90	0	0
T12	403465	0	0	0
T17	4228	10	0	0
T18	8874	20	0	0
T19	0	20	0	0
T29	0	20	0	0
T30	0	20	0	0
T31	401755	0	0	0
T32	403892	0	0	0
T33	401920	0	0	0
T34	401718	0	0	0
T35	403752	0	0	0
T36	402426	0	0	0
T37	402323	0	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50687057	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50687057	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

USBAonSuspendReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50687057	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

USBAonWakeAckKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50687057	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

USBDnPUKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50687057	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

USBDpPUKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50687057	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

USBIntrAvEmptyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50687057	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

USBIntrAvOverKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50687057	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

USBIntrDisConKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50687057	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

USBIntrFrameKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50687057	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

USBIntrHostLostKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50687057	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

USBIntrLinkInErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50687057	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

USBIntrLinkOutErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50687057	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

USBIntrLinkResKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50687057	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

USBIntrLinkRstKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50687057	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

USBIntrLinkSusKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50687057	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

USBIntrPktRcvdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50687057	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

USBIntrPktSentKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50687057	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

USBIntrPwrdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50687057	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

USBIntrRxBitstuffErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50687057	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

USBIntrRxCrCErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50687057	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

USBIntrRxFullKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50687057	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

USBIntrRxPidErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50687057	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

USBRefPulseKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50687057	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

USBRefValKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50687057	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

USBRxEnableKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50687057	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

USBTxDKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50687057	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

USBTxSe0Known_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50687057	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0