Unified Coverage Report :: Module :: usbdev_usbif

Module : usbdev_usbif

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.71	96.83	75.44			78.57	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_usbif.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_impl	87.71	96.83	75.44			78.57	100.00

---

Module Instance : tb.dut.usbdev_impl

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.71	96.83	75.44			78.57	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.78	84.21	72.41		31.25	76.03	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.35	90.70	57.14	93.90		75.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_usb_fs_nb_pe	72.80	83.87	72.15		29.73	78.28	100.00
u_usbdev_linkstate	70.19	79.69	71.76		33.33	66.18	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : usbdev_usbif

	Line No.	Total	Covered	Percent
TOTAL		63	61	96.83
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	129	0	0
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
ALWAYS	137	6	6	100.00
CONT_ASSIGN	159	1	1	100.00
ALWAYS	163	6	6	100.00
ALWAYS	175	8	8	100.00
CONT_ASSIGN	190	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
ALWAYS	211	3	3	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
CONT_ASSIGN	229	1	1	100.00
CONT_ASSIGN	239	0	0
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
ALWAYS	246	2	2	100.00
ALWAYS	253	3	3	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	347	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
ALWAYS	351	5	3	60.00
ALWAYS	360	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_usbif.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_usbif.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
129		unreachable
130	1	1
132	1	1
133	1	1
134	1	1
137	1	1
138	1	1
140	1	1
144	1	1
145	1	1
146		unreachable
147		unreachable
149		unreachable
153	1	1
159	1	1
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
175	1	1
176	1	1
177	1	1
178	1	1
180	1	1
181	1	1
183	1	1
184	1	1
			MISSING_ELSE
190	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
200	1	1
202	1	1
208	1	1
211	1	1
212	1	1
214	1	1
219	1	1
221	1	1
223	1	1
224	1	1
229	1	1
239		unreachable
240	1	1
244	1	1
246	1	1
247	1	1
253	1	1
254	1	1
256	1	1
260	1	1
261	1	1
263	1	1
347	1	1
348	1	1
351	1	1
352	1	1
353	0	1
354	1	1
355	0	1
			MISSING_ELSE
360	1	1
361	1	1
363	1	1

---

Cond Coverage for Module : usbdev_usbif

	Total	Covered	Percent
Conditions	57	43	75.44
Logical	57	43	75.44
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION (connect_en_i & usb_sense_i)
             ------1-----   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION (out_endpoint_val_o ? out_ep_current : '0)
             ---------1--------

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       133
 EXPRESSION (((~connect_en_i)) | link_reset)
             --------1--------   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       137
 EXPRESSION (out_ep_acked || out_ep_rollback)
             ------1-----    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       159
 EXPRESSION (out_ep_data_put & (int'(out_max_used_q) < (MaxPktSizeByte - 1)) & (out_ep_put_addr[1:0] == 2'b11))
             -------1-------   ----------------------2----------------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable	T12,T13
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       159
 SUB-EXPRESSION (out_ep_put_addr[1:0] == 2'b11)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       190
 EXPRESSION (av_rvalid_i & (std_write_q | (((~out_max_used_q[PktW])) & (out_max_used_q[1:0] != 2'b11) & out_ep_acked)))
             -----1-----   ---------------------------------------------2---------------------------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       190
 SUB-EXPRESSION (std_write_q | (((~out_max_used_q[PktW])) & (out_max_used_q[1:0] != 2'b11) & out_ep_acked))
                 -----1-----   -------------------------------------2-------------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       190
 SUB-EXPRESSION (((~out_max_used_q[PktW])) & (out_max_used_q[1:0] != 2'b11) & out_ep_acked)
                 ------------1------------   ---------------2--------------   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13
1	0	1	Covered	T42,T43,T44
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       190
 SUB-EXPRESSION (out_max_used_q[1:0] != 2'b11)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       194
 EXPRESSION (mem_write_o ? mem_waddr : mem_raddr)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION (mem_read | mem_write_o)
             ----1---   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       221
 EXPRESSION (((~rx_wready_i)) | ((~av_rvalid_i)))
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       229
 EXPRESSION (current_setup & rx_wvalid_o)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       240
 EXPRESSION (in_endpoint_val_o ? in_ep_current : '0)
             --------1--------

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       244
 EXPRESSION ({1'b0, in_ep_get_addr} == in_size_i)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       261
 EXPRESSION (pkt_start_rd | (in_ep_data_get & (in_ep_get_addr[1:0] == 2'b0)))
             ------1-----   ------------------------2-----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       261
 SUB-EXPRESSION (in_ep_data_get & (in_ep_get_addr[1:0] == 2'b0))
                 -------1------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       261
 SUB-EXPRESSION (in_ep_get_addr[1:0] == 2'b0)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       263
 EXPRESSION (in_ep_get_addr[1] ? (in_ep_get_addr[0] ? mem_rdata_i[31:24] : mem_rdata_i[23:16]) : (in_ep_get_addr[0] ? mem_rdata_i[15:8] : mem_rdata_i[7:0]))
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       263
 SUB-EXPRESSION (in_ep_get_addr[0] ? mem_rdata_i[31:24] : mem_rdata_i[23:16])
                 --------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       263
 SUB-EXPRESSION (in_ep_get_addr[0] ? mem_rdata_i[15:8] : mem_rdata_i[7:0])
                 --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       348
 EXPRESSION (frame_q != frame_d)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Module : usbdev_usbif

	Line No.	Total	Covered	Percent
Branches		28	22	78.57
TERNARY	130	1	1	100.00
TERNARY	194	2	2	100.00
TERNARY	240	1	1	100.00
TERNARY	263	4	1	25.00
IF	137	3	3	100.00
CASE	165	5	4	80.00
IF	175	3	3	100.00
IF	211	2	2	100.00
IF	253	2	2	100.00
IF	352	3	1	33.33
IF	360	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_usbif.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_usbif.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	(out_endpoint_val_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	194	(mem_write_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	240	(in_endpoint_val_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	263	(in_ep_get_addr[1]) ? 
-2-:	263	(in_ep_get_addr[0]) ? 
-3-:	263	(in_ep_get_addr[0]) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Not Covered
1	0	-	Not Covered
0	-	1	Not Covered
0	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	137	if ((out_ep_acked || out_ep_rollback))
-2-:	140	if (out_ep_data_put)
-3-:	144	if ((int'(out_max_used_q) < (MaxPktSizeByte - 1)))
-4-:	146	if ((int'(out_max_used_q) < (MaxPktSizeByte + 1)))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	1	-	Covered	T1,T2,T3
0	1	0	1	Unreachable	T12,T13
0	1	0	0	Unreachable
0	0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	case (out_ep_put_addr[1:0])

Branches:

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3
2	Covered	T1,T2,T3
3	Covered	T1,T2,T3
default	Not Covered

	LineNo.	Expression
-1-:	175	if ((!rst_ni))
-2-:	183	if (out_ep_data_put)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	211	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	352	if (sof_valid_o)
-2-:	354	if (do_internal_sof)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	360	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : usbdev_usbif

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ParamAVFifoWidthValid	131	131	0	0
ParamMaxPktSizeByteValid	131	131	0	0
ParamNBufValid	131	131	0	0
ParamNEndpointsValid	131	131	0	0
ParamRXFifoWidthValid	131	131	0	0
ParamSramAwValid	131	131	0	0

ParamAVFifoWidthValid

Name	Attempts	Real Successes	Failures	Incomplete
Total	131	131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

ParamMaxPktSizeByteValid

Name	Attempts	Real Successes	Failures	Incomplete
Total	131	131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

ParamNBufValid

Name	Attempts	Real Successes	Failures	Incomplete
Total	131	131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

ParamNEndpointsValid

Name	Attempts	Real Successes	Failures	Incomplete
Total	131	131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

ParamRXFifoWidthValid

Name	Attempts	Real Successes	Failures	Incomplete
Total	131	131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

ParamSramAwValid

Name	Attempts	Real Successes	Failures	Incomplete
Total	131	131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0