Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.49	96.38	62.63	93.46		85.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	115191381	17420	0	0
ep_in_enable_rd_A	115191381	1080	0	0
ep_out_enable_rd_A	115191381	1284	0	0
in_iso_rd_A	115191381	1334	0	0
intr_enable_rd_A	115191381	1893	0	0
out_iso_rd_A	115191381	1220	0	0
phy_config_rd_A	115191381	997	0	0
phy_pins_drive_rd_A	115191381	1103	0	0
rxenable_setup_rd_A	115191381	1480	0	0
set_nak_out_rd_A	115191381	1430	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115191381	17420	0	0
T38	9281	747	0	0
T39	9788	516	0	0
T40	9865	232	0	0
T118	14800	3	0	0
T119	3978	669	0	0
T120	7771	755	0	0
T121	23743	8	0	0
T122	11116	812	0	0
T123	7254	724	0	0
T143	14271	3	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115191381	1080	0	0
T47	6418	14	0	0
T116	9778	102	0	0
T118	14800	144	0	0
T131	11611	23	0	0
T135	9567	87	0	0
T141	7406	40	0	0
T143	14271	162	0	0
T162	6800	23	0	0
T163	16235	158	0	0
T164	2473	2	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115191381	1284	0	0
T47	6418	28	0	0
T116	9778	91	0	0
T118	14800	312	0	0
T131	11611	32	0	0
T135	9567	109	0	0
T141	7406	33	0	0
T143	14271	242	0	0
T162	6800	40	0	0
T163	16235	131	0	0
T165	14667	159	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115191381	1334	0	0
T47	6418	21	0	0
T116	9778	109	0	0
T118	14800	165	0	0
T131	11611	27	0	0
T135	9567	95	0	0
T141	7406	25	0	0
T143	14271	315	0	0
T162	6800	14	0	0
T163	16235	128	0	0
T164	2473	39	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115191381	1893	0	0
T47	6418	26	0	0
T116	9778	91	0	0
T118	14800	408	0	0
T131	11611	33	0	0
T135	9567	115	0	0
T141	7406	92	0	0
T143	14271	294	0	0
T162	6800	64	0	0
T163	16235	183	0	0
T166	14527	6	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115191381	1220	0	0
T47	6418	13	0	0
T116	9778	78	0	0
T118	14800	221	0	0
T131	11611	57	0	0
T135	9567	103	0	0
T141	7406	38	0	0
T143	14271	134	0	0
T162	6800	40	0	0
T163	16235	115	0	0
T164	2473	42	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115191381	997	0	0
T47	6418	32	0	0
T116	9778	116	0	0
T118	14800	124	0	0
T131	11611	25	0	0
T135	9567	120	0	0
T141	7406	90	0	0
T143	14271	98	0	0
T162	6800	43	0	0
T163	16235	59	0	0
T167	13192	8	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115191381	1103	0	0
T47	6418	36	0	0
T116	9778	131	0	0
T118	14800	168	0	0
T131	11611	29	0	0
T135	9567	84	0	0
T141	7406	39	0	0
T143	14271	220	0	0
T162	6800	18	0	0
T163	16235	100	0	0
T164	2473	6	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115191381	1480	0	0
T47	6418	43	0	0
T116	9778	111	0	0
T118	14800	276	0	0
T131	11611	65	0	0
T135	9567	85	0	0
T141	7406	37	0	0
T143	14271	291	0	0
T162	6800	11	0	0
T163	16235	159	0	0
T166	14527	5	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115191381	1430	0	0
T47	6418	4	0	0
T116	9778	137	0	0
T118	14800	122	0	0
T131	11611	22	0	0
T135	9567	114	0	0
T141	7406	56	0	0
T143	14271	283	0	0
T162	6800	7	0	0
T163	16235	170	0	0
T164	2473	48	0	0