Unified Coverage Report :: Module :: usbdev

Module : usbdev

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.49	96.38	62.63	93.46		85.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	87.49	96.38	62.63	93.46		85.00	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.49	96.38	62.63	93.46		85.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.79	95.98	85.41	96.94	45.31	93.76	97.36

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_event	100.00	100.00				100.00
gen_no_stubbed_memory.u_memory_1p	98.96	95.83	100.00			100.00	100.00
gen_no_stubbed_memory.u_tlul2sram	83.66	85.71	70.51			78.41	100.00
i_usbdev_iomux	66.67	88.89	44.44			83.33	50.00
intr_av_out_empty	81.39	90.00	55.56			80.00	100.00
intr_av_overflow	81.25	100.00	25.00			100.00	100.00
intr_av_setup_empty	81.39	90.00	55.56			80.00	100.00
intr_disconnected	87.50	100.00	50.00			100.00	100.00
intr_frame	81.25	100.00	25.00			100.00	100.00
intr_host_lost	81.25	100.00	25.00			100.00	100.00
intr_hw_pkt_received	86.94	90.00	77.78			80.00	100.00
intr_hw_pkt_sent	84.17	90.00	66.67			80.00	100.00
intr_link_in_err	81.25	100.00	25.00			100.00	100.00
intr_link_out_err	89.58	100.00	58.33			100.00	100.00
intr_link_reset	89.58	100.00	58.33			100.00	100.00
intr_link_resume	81.25	100.00	25.00			100.00	100.00
intr_link_suspend	81.25	100.00	25.00			100.00	100.00
intr_powered	89.58	100.00	58.33			100.00	100.00
intr_rx_bitstuff_err	81.25	100.00	25.00			100.00	100.00
intr_rx_crc_err	81.25	100.00	25.00			100.00	100.00
intr_rx_full	73.06	90.00	22.22			80.00	100.00
intr_rx_pid_err	81.25	100.00	25.00			100.00	100.00
tlul_assert_device	95.24	100.00				85.71	100.00
u_reg	95.17	98.00	93.09	100.00		97.68	87.10
usbdev_avoutfifo	82.08	95.00	58.33			75.00	100.00
usbdev_avsetupfifo	82.08	95.00	58.33			75.00	100.00
usbdev_csr_assert	100.00						100.00
usbdev_impl	80.55	91.16	82.62		45.31	83.65	100.00
usbdev_rxfifo	83.58	95.00	61.54			77.78	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : usbdev

	Line No.	Total	Covered	Percent
TOTAL		138	133	96.38
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
ALWAYS	211	5	5	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	297	1	1	100.00
CONT_ASSIGN	302	1	1	100.00
CONT_ASSIGN	305	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	333	1	1	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	337	1	1	100.00
CONT_ASSIGN	341	1	0	0.00
ALWAYS	364	0	0
ALWAYS	364	3	3	100.00
ALWAYS	372	0	0
ALWAYS	372	4	4	100.00
ALWAYS	381	0	0
ALWAYS	381	3	3	100.00
ALWAYS	388	0	0
ALWAYS	388	3	3	100.00
ALWAYS	395	0	0
ALWAYS	395	3	3	100.00
ALWAYS	402	0	0
ALWAYS	402	2	2	100.00
CONT_ASSIGN	409	1	0	0.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	418	1	0	0.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
ALWAYS	426	3	3	100.00
ALWAYS	433	0	0
ALWAYS	433	3	3	100.00
ALWAYS	442	3	3	100.00
ALWAYS	454	3	3	100.00
ALWAYS	461	0	0
ALWAYS	461	3	3	100.00
ALWAYS	468	10	10	100.00
ALWAYS	486	0	0
ALWAYS	486	3	3	100.00
ALWAYS	494	0	0
ALWAYS	494	3	3	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	506	1	1	100.00
CONT_ASSIGN	617	1	1	100.00
CONT_ASSIGN	618	1	1	100.00
CONT_ASSIGN	620	1	1	100.00
CONT_ASSIGN	621	1	1	100.00
CONT_ASSIGN	639	1	1	100.00
CONT_ASSIGN	642	1	1	100.00
ALWAYS	648	0	0
ALWAYS	648	8	8	100.00
CONT_ASSIGN	728	1	1	100.00
CONT_ASSIGN	729	1	1	100.00
CONT_ASSIGN	730	1	1	100.00
CONT_ASSIGN	731	1	1	100.00
CONT_ASSIGN	739	1	1	100.00
ALWAYS	748	8	8	100.00
CONT_ASSIGN	762	1	1	100.00
CONT_ASSIGN	763	0	0
CONT_ASSIGN	766	1	1	100.00
CONT_ASSIGN	767	1	1	100.00
CONT_ASSIGN	824	1	1	100.00
CONT_ASSIGN	825	1	1	100.00
CONT_ASSIGN	829	1	1	100.00
CONT_ASSIGN	1092	1	1	100.00
CONT_ASSIGN	1093	1	1	100.00
CONT_ASSIGN	1094	1	1	100.00
CONT_ASSIGN	1095	1	1	100.00
CONT_ASSIGN	1135	1	1	100.00
CONT_ASSIGN	1138	1	1	100.00
CONT_ASSIGN	1147	1	1	100.00
ALWAYS	1150	5	3	60.00
ALWAYS	1159	3	3	100.00
CONT_ASSIGN	1172	1	1	100.00
CONT_ASSIGN	1175	1	1	100.00
CONT_ASSIGN	1182	1	1	100.00
ALWAYS	1186	3	3	100.00
CONT_ASSIGN	1193	1	1	100.00
CONT_ASSIGN	1198	1	1	100.00
CONT_ASSIGN	1200	1	1	100.00
CONT_ASSIGN	1208	0	0
CONT_ASSIGN	1210	0	0
CONT_ASSIGN	1212	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
122	1	1
209	1	1
211	1	1
212	1	1
214	1	1
215	1	1
217	1	1
244	1	1
245	1	1
247	1	1
249	1	1
297	1	1
302	1	1
305	1	1
308	1	1
333	1	1
334	1	1
335	1	1
336	1	1
337	1	1
341	0	1
364	1	1
365	1	1
366	1	1
372	1	1
373	1	1
374	1	1
375	1	1
381	1	1
382	1	1
383	1	1
388	1	1
389	1	1
390	1	1
395	1	1
396	1	1
397	1	1
402	1	1
403	1	1
409	0	1
410	1	1
411	1	1
413	1	1
418	0	1
419	1	1
420	1	1
422	1	1
426	1	1
427	1	1
428	1	1
			MISSING_ELSE
433	1	1
434	1	1
435	1	1
442	1	1
443	1	1
444	1	1
454	1	1
455	1	1
456	1	1
			MISSING_ELSE
461	1	1
462	1	1
463	1	1
468	1	1
469	1	1
470	1	1
471	1	1
472	1	1
474	1	1
476	1	1
477	1	1
478	1	1
480	1	1
			MISSING_ELSE
486	1	1
487	1	1
488	1	1
494	1	1
495	1	1
496	1	1
504	1	1
505	1	1
506	1	1
617	1	1
618	1	1
620	1	1
621	1	1
639	1	1
642	1	1
648	1	1
649	1	1
650	1	1
651	1	1
652	1	1
653	1	1
655	1	1
656	1	1
728	1	1
729	1	1
730	1	1
731	1	1
739	1	1
748	1	1
749	1	1
750	1	1
751	1	1
753	1	1
754	1	1
756	1	1
757	1	1
			MISSING_ELSE
762	1	1
763		unreachable
766	1	1
767	1	1
824	1	1
825	1	1
829	1	1
1092	1	1
1093	1	1
1094	1	1
1095	1	1
1135	1	1
1138	1	1
1147	1	1
1150	1	1
1151	1	1
1152	0	1
1153	1	1
1154	0	1
			MISSING_ELSE
1159	1	1
1160	1	1
1162	1	1
1172	1	1
1175	1	1
1182	1	1
1186	1	1
1187	1	1
1189	1	1
1193	1	1
1198	1	1
1200	1	1
1208		unreachable
1210		unreachable
1212		unreachable

---

Cond Coverage for Module : usbdev

	Total	Covered	Percent
Conditions	99	62	62.63
Logical	99	62	62.63
Non-Logical	0	0
Event	0	0

 LINE       209
 EXPRESSION (ns_cnt == 6'd47)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       244
 EXPRESSION (connect_en & ((~avsetup_rvalid)))
             -----1----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T9,T16
1	1	Covered	T1,T2,T3

 LINE       245
 EXPRESSION (connect_en & ((~avout_rvalid)))
             -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       247
 EXPRESSION ((reg2hw.avsetupbuffer.qe & ((~avsetup_fifo_wready))) | (reg2hw.avoutbuffer.qe & ((~avout_fifo_wready))))
             --------------------------1-------------------------   ------------------------2-----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       247
 SUB-EXPRESSION (reg2hw.avsetupbuffer.qe & ((~avsetup_fifo_wready)))
                 -----------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T9,T16
1	1	Not Covered

 LINE       247
 SUB-EXPRESSION (reg2hw.avoutbuffer.qe & ((~avout_fifo_wready)))
                 ----------1----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Not Covered

 LINE       249
 EXPRESSION (connect_en & ((~rx_fifo_rvalid)))
             -----1----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       297
 EXPRESSION (reg2hw.rxfifo.ep.re | reg2hw.rxfifo.setup.re | reg2hw.rxfifo.size.re | reg2hw.rxfifo.buffer.re)
             ---------1---------   -----------2----------   ----------3----------   -----------4-----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Not Covered
1	0	0	0	Not Covered

 LINE       308
 EXPRESSION (rx_wready & (rx_depth < (RXFifoDepth - 1)))
             ----1----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       409
 EXPRESSION (reg2hw.out_data_toggle.status.qe & reg2hw.out_data_toggle.mask.qe)
             ----------------1---------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       418
 EXPRESSION (reg2hw.in_data_toggle.status.qe & reg2hw.in_data_toggle.mask.qe)
             ---------------1---------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       427
 EXPRESSION (in_ep_xact_end && in_endpoint_val)
             -------1------    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T4,T5,T6

 LINE       455
 EXPRESSION (rx_wvalid && out_endpoint_val)
             ----1----    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T4

 LINE       474
 EXPRESSION (setup_received & out_endpoint_val)
             -------1------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T7,T9,T16

 LINE       478
 EXPRESSION (in_ep_xact_end & in_endpoint_val)
             -------1------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T4,T5,T6

 LINE       496
 EXPRESSION (reg2hw.configin[i].rdy.q | reg2hw.configin[i].pend.q)
             ------------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T4,T5,T6

 LINE       505
 EXPRESSION (cfg_pinflip ? 1'b0 : usb_pullup_en)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       506
 EXPRESSION (((!cfg_pinflip)) ? 1'b0 : usb_pullup_en)
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       621
 EXPRESSION (reg2hw.usbctrl.resume_link_active.qe & reg2hw.usbctrl.resume_link_active.q)
             ------------------1-----------------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       728
 EXPRESSION (usb_mem_b_req | sw_mem_a_req)
             ------1------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T27,T28
1	0	Covered	T1,T2,T4

 LINE       729
 EXPRESSION (usb_mem_b_req ? usb_mem_b_write : sw_mem_a_write)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       730
 EXPRESSION (usb_mem_b_req ? usb_mem_b_addr : sw_mem_a_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       731
 EXPRESSION (usb_mem_b_req ? usb_mem_b_wdata : sw_mem_a_wdata)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       754
 EXPRESSION (usb_mem_b_req & ((!usb_mem_b_write)))
             ------1------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T4,T5,T6

 LINE       762
 EXPRESSION (gen_no_stubbed_memory.mem_rvalid & ((!gen_no_stubbed_memory.mem_rsteering)))
             ----------------1---------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T8,T27,T28

 LINE       767
 EXPRESSION (gen_no_stubbed_memory.mem_b_read_q ? gen_no_stubbed_memory.mem_rdata : gen_no_stubbed_memory.mem_b_rdata_q)
             -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       829
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       1138
 EXPRESSION (use_diff_rcvr & ((~link_suspend)))
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       1147
 EXPRESSION (usb_rcvr_ok_counter_q == '0)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1151
 EXPRESSION (use_diff_rcvr & ((!usb_rx_enable_o)))
             ------1------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       1153
 EXPRESSION (us_tick && (usb_rcvr_ok_counter_q > '0))
             ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       1175
 EXPRESSION (usb_ref_disable ? 1'b0 : event_sof)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       1182
 EXPRESSION (usb_ref_pulse_o ? 1'b1 : ((((!link_active)) || host_lost || usb_ref_disable) ? 1'b0 : usb_ref_val_q))
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       1182
 SUB-EXPRESSION ((((!link_active)) || host_lost || usb_ref_disable) ? 1'b0 : usb_ref_val_q)
                 -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1182
 SUB-EXPRESSION (((!link_active)) || host_lost || usb_ref_disable)
                 --------1-------    ----2----    -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Covered	T1,T2,T3

 LINE       1198
 EXPRESSION (reg2hw.wake_control.suspend_req.qe & reg2hw.wake_control.suspend_req.q)
             -----------------1----------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       1200
 EXPRESSION (reg2hw.wake_control.wake_ack.qe & reg2hw.wake_control.wake_ack.q)
             ---------------1---------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Toggle Coverage for Module : usbdev

	Total	Covered	Percent
Totals	68	60	88.24
Total Bits	428	400	93.46
Total Bits 0->1	214	200	93.46
Total Bits 1->0	214	200	93.46

Ports	68	60	88.24
Port Bits	428	400	93.46
Port Bits 0->1	214	200	93.46
Port Bits 1->0	214	200	93.46

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_aon_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_aon_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T5,T10,T27	Yes	T5,T10,T27	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T4	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T5,T9	Yes	T1,T5,T7	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T38,T39,T40	Yes	T38,T39,T40	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T4	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T41,T42,T43	Yes	T41,T42,T43	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T41,T42,T43	Yes	T41,T42,T43	OUTPUT
cio_usb_dp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_usb_dn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
usb_rx_d_i	No	No		No		INPUT
cio_usb_dp_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T4	OUTPUT
cio_usb_dp_en_o	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
cio_usb_dn_o	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
cio_usb_dn_en_o	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
usb_tx_se0_o	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
usb_tx_d_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T4	OUTPUT
cio_sense_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
usb_dp_pullup_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
usb_dn_pullup_o	Yes	Yes	T44,T45	Yes	T44,T45	OUTPUT
usb_rx_enable_o	Yes	Yes	T46,T38,T47	Yes	T46,T38,T47	OUTPUT
usb_tx_use_d_se0_o	Yes	Yes	T46,T38,T47	Yes	T46,T38,T47	OUTPUT
usb_aon_suspend_req_o	Yes	Yes	T48,T49,T44	Yes	T48,T49,T44	OUTPUT
usb_aon_wake_ack_o	Yes	Yes	T46,T50,T47	Yes	T46,T50,T47	OUTPUT
usb_aon_bus_reset_i	Unreachable	Unreachable		Unreachable		INPUT
usb_aon_sense_lost_i	Unreachable	Unreachable		Unreachable		INPUT
usb_aon_wake_detect_active_i	Unreachable	Unreachable		Unreachable		INPUT
usb_ref_val_o	No	No		No		OUTPUT
usb_ref_pulse_o	No	No		No		OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
intr_pkt_received_o	Yes	Yes	T7,T9,T16	Yes	T7,T9,T16	OUTPUT
intr_pkt_sent_o	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
intr_powered_o	Yes	Yes	T46,T47,T51	Yes	T46,T47,T52	OUTPUT
intr_disconnected_o	Yes	Yes	T46,T47,T40	Yes	T46,T50,T47	OUTPUT
intr_host_lost_o	No	No		No		OUTPUT
intr_link_reset_o	Yes	Yes	T48,T44,T45	Yes	T48,T44,T45	OUTPUT
intr_link_suspend_o	Yes	Yes	T44	Yes	T44	OUTPUT
intr_link_resume_o	Yes	Yes	T48,T44,T45	Yes	T48,T44,T45	OUTPUT
intr_av_out_empty_o	Yes	Yes	T53,T44	Yes	T53,T44	OUTPUT
intr_rx_full_o	Yes	Yes	T53,T48,T44	Yes	T53,T48,T44	OUTPUT
intr_av_overflow_o	Yes	Yes	T53,T44	Yes	T53,T44	OUTPUT
intr_link_in_err_o	Yes	Yes	T49,T45	Yes	T49,T45	OUTPUT
intr_link_out_err_o	Yes	Yes	T44	Yes	T44	OUTPUT
intr_rx_crc_err_o	Yes	Yes	T44	Yes	T44	OUTPUT
intr_rx_pid_err_o	Yes	Yes	T48	Yes	T48	OUTPUT
intr_rx_bitstuff_err_o	Yes	Yes	T48,T45	Yes	T48,T45	OUTPUT
intr_frame_o	Yes	Yes	T48,T45	Yes	T48,T45	OUTPUT
intr_av_setup_empty_o	Yes	Yes	T53,T48	Yes	T53,T48	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : usbdev

	Line No.	Total	Covered	Percent
Branches		40	34	85.00
TERNARY	505	2	1	50.00
TERNARY	506	2	1	50.00
TERNARY	1175	2	1	50.00
TERNARY	1182	3	2	66.67
TERNARY	729	2	2	100.00
TERNARY	730	2	2	100.00
TERNARY	731	2	2	100.00
TERNARY	767	2	2	100.00
IF	211	3	3	100.00
IF	427	2	2	100.00
IF	455	2	2	100.00
IF	470	4	4	100.00
IF	651	2	2	100.00
IF	1151	3	1	33.33
IF	1159	2	2	100.00
IF	1186	2	2	100.00
IF	748	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	505	(cfg_pinflip) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	506	((!cfg_pinflip)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	1175	(usb_ref_disable) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1182	(usb_ref_pulse_o) ? 
-2-:	1182	((((!link_active) || host_lost) || usb_ref_disable)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	729	(usb_mem_b_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	730	(usb_mem_b_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	731	(usb_mem_b_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	767	(gen_no_stubbed_memory.mem_b_read_q) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	211	if ((!rst_n))
-2-:	214	if (us_tick)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	427	if ((in_ep_xact_end && in_endpoint_val))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	455	if ((rx_wvalid && out_endpoint_val))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	470	if (event_link_reset)
-2-:	474	if ((setup_received & out_endpoint_val))
-3-:	478	if ((in_ep_xact_end & in_endpoint_val))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T7,T9,T16
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	651	if (((setup_received && out_endpoint_val) && (out_endpoint == 4'((unsigned'(i))))))

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1151	if ((use_diff_rcvr & (!usb_rx_enable_o)))
-2-:	1153	if ((us_tick && (usb_rcvr_ok_counter_q > '0)))

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1159	if ((!rst_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1186	if ((!rst_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	748	if ((!rst_ni))
-2-:	756	if (gen_no_stubbed_memory.mem_b_read_q)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : usbdev

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	35	35	100.00	35	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	35	35	100.00	35	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertsKnown_A	114481951	114425631	0	0
CIODnEnKnown_A	114481951	114425631	0	0
CIODnKnown_A	114481951	114425631	0	0
CIODpEnKnown_A	114481951	114425631	0	0
CIODpKnown_A	114481951	114425631	0	0
FpvSecCmRegWeOnehotCheck_A	114481951	80	0	0
TlOAReadyKnown_A	114481951	114425631	0	0
TlODValidKnown_A	114481951	114425631	0	0
USBAonSuspendReqKnown_A	114481951	114425631	0	0
USBAonWakeAckKnown_A	114481951	114425631	0	0
USBDnPUKnown_A	114481951	114425631	0	0
USBDpPUKnown_A	114481951	114425631	0	0
USBIntrAvOutEmptyKnown_A	114481951	114425631	0	0
USBIntrAvOverKnown_A	114481951	114425631	0	0
USBIntrAvSetupEmptyKnown_A	114481951	114425631	0	0
USBIntrDisConKnown_A	114481951	114425631	0	0
USBIntrFrameKnown_A	114481951	114425631	0	0
USBIntrHostLostKnown_A	114481951	114425631	0	0
USBIntrLinkInErrKnown_A	114481951	114425631	0	0
USBIntrLinkOutErrKnown_A	114481951	114425631	0	0
USBIntrLinkResKnown_A	114481951	114425631	0	0
USBIntrLinkRstKnown_A	114481951	114425631	0	0
USBIntrLinkSusKnown_A	114481951	114425631	0	0
USBIntrPktRcvdKnown_A	114481951	114425631	0	0
USBIntrPktSentKnown_A	114481951	114425631	0	0
USBIntrPwrdKnown_A	114481951	114425631	0	0
USBIntrRxBitstuffErrKnown_A	114481951	114425631	0	0
USBIntrRxCrCErrKnown_A	114481951	114425631	0	0
USBIntrRxFullKnown_A	114481951	114425631	0	0
USBIntrRxPidErrKnown_A	114481951	114425631	0	0
USBRefPulseKnown_A	114481951	114425631	0	0
USBRefValKnown_A	114481951	114425631	0	0
USBRxEnableKnown_A	114481951	114425631	0	0
USBTxDKnown_A	114481951	114425631	0	0
USBTxSe0Known_A	114481951	114425631	0	0

AlertsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

CIODnEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

CIODnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

CIODpEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

CIODpKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	80	0	0
T20	405521	0	0	0
T36	401893	0	0	0
T41	13265	20	0	0
T42	0	20	0	0
T43	0	20	0	0
T54	0	10	0	0
T55	0	10	0	0
T56	402021	0	0	0
T57	405051	0	0	0
T58	402615	0	0	0
T59	401632	0	0	0
T60	406247	0	0	0
T61	405721	0	0	0
T62	403046	0	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

USBAonSuspendReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

USBAonWakeAckKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

USBDnPUKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

USBDpPUKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

USBIntrAvOutEmptyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

USBIntrAvOverKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

USBIntrAvSetupEmptyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

USBIntrDisConKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

USBIntrFrameKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

USBIntrHostLostKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

USBIntrLinkInErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

USBIntrLinkOutErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

USBIntrLinkResKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

USBIntrLinkRstKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

USBIntrLinkSusKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

USBIntrPktRcvdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

USBIntrPktSentKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

USBIntrPwrdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

USBIntrRxBitstuffErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

USBIntrRxCrCErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

USBIntrRxFullKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

USBIntrRxPidErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

USBRefPulseKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

USBRefValKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

USBRxEnableKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

USBTxDKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

USBTxSe0Known_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0