Unified Coverage Report :: Module Instance :: tb.dut.usbdev_avsetupfifo

Module Instance : tb.dut.usbdev_avsetupfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	100.00	58.33			75.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.08	95.00	58.33			75.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.49	96.38	62.63	93.46		85.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00

Module Instance : tb.dut.usbdev_avoutfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	100.00	58.33			75.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.08	95.00	58.33			75.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.49	96.38	62.63	93.46		85.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00

Module Instance : tb.dut.usbdev_rxfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.38	100.00	61.54			80.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.58	95.00	61.54			77.78	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.49	96.38	62.63	93.46		85.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	182	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
182	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Covered	Percent
Conditions	24	14	58.33
Logical	24	14	58.33
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (3'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T7,T9,T16

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T7,T9,T16
1	1	0	Not Covered
1	1	1	Covered	T7,T9,T16

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T9,T16

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
TERNARY	88	3	1	33.33
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Not Covered

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	114481951	19174432	0	0
DepthKnown_A	114481951	114425631	0	0
RvalidKnown_A	114481951	114425631	0	0
WreadyKnown_A	114481951	114425631	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	114481951	19174432	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	19174432	0	0
T7	401777	400030	0	0
T8	402181	0	0	0
T9	401744	399886	0	0
T10	403731	0	0	0
T11	404695	0	0	0
T12	404076	0	0	0
T13	403483	0	0	0
T14	402501	0	0	0
T16	0	398713	0	0
T27	401654	0	0	0
T28	401592	0	0	0
T56	0	399536	0	0
T59	0	399819	0	0
T63	0	399987	0	0
T64	0	398981	0	0
T65	0	399924	0	0
T66	0	399162	0	0
T67	0	399869	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	19174432	0	0
T7	401777	400030	0	0
T8	402181	0	0	0
T9	401744	399886	0	0
T10	403731	0	0	0
T11	404695	0	0	0
T12	404076	0	0	0
T13	403483	0	0	0
T14	402501	0	0	0
T16	0	398713	0	0
T27	401654	0	0	0
T28	401592	0	0	0
T56	0	399536	0	0
T59	0	399819	0	0
T63	0	399987	0	0
T64	0	398981	0	0
T65	0	399924	0	0
T66	0	399162	0	0
T67	0	399869	0	0

Line Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	182	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
182	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Covered	Percent
Conditions	24	14	58.33
Logical	24	14	58.33
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (4'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
TERNARY	88	3	1	33.33
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Not Covered

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	114481951	75081482	0	0
DepthKnown_A	114481951	114425631	0	0
RvalidKnown_A	114481951	114425631	0	0
WreadyKnown_A	114481951	114425631	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	114481951	75081482	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	75081482	0	0
T1	402707	402187	0	0
T2	403470	402413	0	0
T3	401610	0	0	0
T4	404958	404379	0	0
T5	402645	401994	0	0
T6	405548	401701	0	0
T7	401777	0	0	0
T8	402181	399263	0	0
T9	401744	0	0	0
T10	403731	401657	0	0
T11	0	404180	0	0
T27	0	399945	0	0
T28	0	400058	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	75081482	0	0
T1	402707	402187	0	0
T2	403470	402413	0	0
T3	401610	0	0	0
T4	404958	404379	0	0
T5	402645	401994	0	0
T6	405548	401701	0	0
T7	401777	0	0	0
T8	402181	399263	0	0
T9	401744	0	0	0
T10	403731	401657	0	0
T11	0	404180	0	0
T27	0	399945	0	0
T28	0	400058	0	0

Line Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Covered	Percent
Conditions	26	16	61.54
Logical	26	16	61.54
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (4'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
Branches		10	8	80.00
TERNARY	88	3	1	33.33
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Not Covered

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	114481951	27682	0	0
DepthKnown_A	114481951	114425631	0	0
RvalidKnown_A	114481951	114425631	0	0
WreadyKnown_A	114481951	114425631	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	114481951	27682	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	27682	0	0
T1	402707	151	0	0
T2	403470	133	0	0
T3	401610	0	0	0
T4	404958	109	0	0
T5	402645	114	0	0
T6	405548	119	0	0
T7	401777	110	0	0
T8	402181	109	0	0
T9	401744	109	0	0
T10	403731	133	0	0
T11	0	147	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	114425631	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	114481951	27682	0	0
T1	402707	151	0	0
T2	403470	133	0	0
T3	401610	0	0	0
T4	404958	109	0	0
T5	402645	114	0	0
T6	405548	119	0	0
T7	401777	110	0	0
T8	402181	109	0	0
T9	401744	109	0	0
T10	403731	133	0	0
T11	0	147	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	115191381	212468	0	0
DepthKnown_A	115191381	115110243	0	0
RvalidKnown_A	115191381	115110243	0	0
WreadyKnown_A	115191381	115110243	0	0
gen_passthru_fifo.paramCheckPass	392	392	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115191381	212468	0	0
T1	402707	12	0	0
T2	403470	12	0	0
T3	401610	7	0	0
T4	404958	18	0	0
T5	402645	18	0	0
T6	405548	15	0	0
T7	401777	9	0	0
T8	402181	9	0	0
T9	401744	9	0	0
T10	403731	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115191381	115110243	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115191381	115110243	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115191381	115110243	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	392	392	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	115191381	195025	0	0
DepthKnown_A	115191381	115110243	0	0
RvalidKnown_A	115191381	115110243	0	0
WreadyKnown_A	115191381	115110243	0	0
gen_passthru_fifo.paramCheckPass	392	392	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115191381	195025	0	0
T1	402707	43	0	0
T2	403470	12	0	0
T3	401610	25	0	0
T4	404958	70	0	0
T5	402645	45	0	0
T6	405548	84	0	0
T7	401777	9	0	0
T8	402181	9	0	0
T9	401744	36	0	0
T10	403731	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115191381	115110243	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115191381	115110243	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115191381	115110243	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	392	392	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	115191381	47870	0	0
DepthKnown_A	115191381	115110243	0	0
RvalidKnown_A	115191381	115110243	0	0
WreadyKnown_A	115191381	115110243	0	0
gen_passthru_fifo.paramCheckPass	392	392	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115191381	47870	0	0
T8	402181	2	0	0
T9	401744	0	0	0
T10	403731	0	0	0
T11	404695	0	0	0
T12	404076	0	0	0
T13	403483	0	0	0
T14	402501	0	0	0
T17	401187	0	0	0
T27	401654	2	0	0
T28	401592	2	0	0
T29	0	2	0	0
T30	0	2	0	0
T33	0	2	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	0	2	0	0
T37	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115191381	115110243	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115191381	115110243	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115191381	115110243	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	392	392	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	115191381	46273	0	0
DepthKnown_A	115191381	115110243	0	0
RvalidKnown_A	115191381	115110243	0	0
WreadyKnown_A	115191381	115110243	0	0
gen_passthru_fifo.paramCheckPass	392	392	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115191381	46273	0	0
T8	402181	2	0	0
T9	401744	0	0	0
T10	403731	0	0	0
T11	404695	0	0	0
T12	404076	0	0	0
T13	403483	0	0	0
T14	402501	0	0	0
T17	401187	0	0	0
T27	401654	2	0	0
T28	401592	2	0	0
T29	0	2	0	0
T30	0	7	0	0
T33	0	2	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	0	2	0	0
T37	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115191381	115110243	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115191381	115110243	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115191381	115110243	0	0
T1	402707	402548	0	0
T2	403470	403291	0	0
T3	401610	401455	0	0
T4	404958	404782	0	0
T5	402645	402503	0	0
T6	405548	405386	0	0
T7	401777	401520	0	0
T8	402181	401975	0	0
T9	401744	401554	0	0
T10	403731	403578	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	392	392	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0