Line Coverage for Module :
usb_fs_nb_in_pe
| Line No. | Total | Covered | Percent |
TOTAL | | 108 | 91 | 84.26 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 119 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
CONT_ASSIGN | 143 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
ALWAYS | 169 | 49 | 34 | 69.39 |
ALWAYS | 271 | 3 | 3 | 100.00 |
ALWAYS | 279 | 3 | 3 | 100.00 |
ALWAYS | 288 | 8 | 8 | 100.00 |
ALWAYS | 301 | 6 | 6 | 100.00 |
ALWAYS | 313 | 7 | 7 | 100.00 |
ALWAYS | 328 | 7 | 5 | 71.43 |
CONT_ASSIGN | 342 | 1 | 1 | 100.00 |
ALWAYS | 345 | 5 | 5 | 100.00 |
ALWAYS | 355 | 5 | 5 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_in_pe.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_in_pe.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
105 |
1 |
1 |
119 |
1 |
1 |
120 |
1 |
1 |
122 |
1 |
1 |
128 |
1 |
1 |
132 |
1 |
1 |
136 |
1 |
1 |
142 |
1 |
1 |
143 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
154 |
1 |
1 |
156 |
1 |
1 |
159 |
1 |
1 |
169 |
1 |
1 |
170 |
1 |
1 |
171 |
1 |
1 |
172 |
1 |
1 |
173 |
1 |
1 |
174 |
1 |
1 |
175 |
1 |
1 |
177 |
1 |
1 |
178 |
1 |
1 |
181 |
1 |
1 |
186 |
1 |
1 |
188 |
1 |
1 |
193 |
0 |
1 |
194 |
0 |
1 |
195 |
1 |
1 |
196 |
0 |
1 |
197 |
0 |
1 |
198 |
1 |
1 |
199 |
1 |
1 |
200 |
1 |
1 |
202 |
0 |
1 |
203 |
0 |
1 |
209 |
1 |
1 |
210 |
1 |
1 |
211 |
0 |
1 |
212 |
0 |
1 |
214 |
1 |
1 |
215 |
0 |
1 |
217 |
1 |
1 |
221 |
1 |
1 |
226 |
1 |
1 |
227 |
1 |
1 |
|
|
|
MISSING_ELSE |
235 |
1 |
1 |
237 |
1 |
1 |
238 |
1 |
1 |
239 |
1 |
1 |
240 |
0 |
1 |
241 |
0 |
1 |
243 |
1 |
1 |
248 |
1 |
1 |
249 |
1 |
1 |
250 |
1 |
1 |
251 |
1 |
1 |
252 |
0 |
1 |
253 |
0 |
1 |
254 |
1 |
1 |
255 |
0 |
1 |
256 |
0 |
1 |
258 |
1 |
1 |
271 |
1 |
1 |
272 |
1 |
1 |
274 |
1 |
1 |
279 |
1 |
1 |
280 |
1 |
1 |
282 |
1 |
1 |
288 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
291 |
1 |
1 |
292 |
1 |
1 |
293 |
1 |
1 |
295 |
1 |
1 |
296 |
1 |
1 |
301 |
1 |
1 |
302 |
1 |
1 |
304 |
1 |
1 |
305 |
1 |
1 |
306 |
1 |
1 |
307 |
1 |
1 |
|
|
|
MISSING_ELSE |
313 |
1 |
1 |
314 |
1 |
1 |
315 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
319 |
1 |
1 |
321 |
1 |
1 |
328 |
1 |
1 |
330 |
1 |
1 |
331 |
0 |
1 |
332 |
1 |
1 |
333 |
1 |
1 |
|
|
|
MISSING_ELSE |
336 |
1 |
1 |
337 |
0 |
1 |
|
|
|
MISSING_ELSE |
342 |
1 |
1 |
345 |
1 |
1 |
346 |
1 |
1 |
347 |
1 |
1 |
348 |
1 |
1 |
350 |
1 |
1 |
355 |
1 |
1 |
356 |
1 |
1 |
358 |
1 |
1 |
359 |
1 |
1 |
361 |
1 |
1 |
Cond Coverage for Module :
usb_fs_nb_in_pe
| Total | Covered | Percent |
Conditions | 70 | 58 | 82.86 |
Logical | 70 | 58 | 82.86 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 122
EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && (rx_pid_type == UsbPidTypeToken) && (rx_addr_i == dev_addr_i))
------1----- -------2------ ----------------3--------------- ------------4------------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | Covered | T1,T2,T4 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 122
SUB-EXPRESSION (rx_pid_type == UsbPidTypeToken)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 122
SUB-EXPRESSION (rx_addr_i == dev_addr_i)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 128
EXPRESSION (token_received && (rx_pid == UsbPidSetup))
-------1------ -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T7,T9 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T3,T7,T9 |
LINE 128
SUB-EXPRESSION (rx_pid == UsbPidSetup)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T7,T9 |
LINE 132
EXPRESSION (token_received && (rx_pid == UsbPidIn))
-------1------ ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T5,T6 |
LINE 132
SUB-EXPRESSION (rx_pid == UsbPidIn)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T5,T6 |
LINE 136
EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && (rx_pid == UsbPidAck))
------1----- -------2------ ----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T4,T5,T6 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T4,T5,T6 |
LINE 136
SUB-EXPRESSION (rx_pid == UsbPidAck)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T5,T6 |
LINE 143
EXPRESSION (ep_in_hw ? rx_endp_i : '0)
----1---
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 154
EXPRESSION (in_ep_enabled_i[in_ep_index_d] & ep_in_hw)
---------------1-------------- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T5,T6 |
LINE 156
EXPRESSION (in_ep_has_data_i[in_ep_index] & ((~in_ep_data_done_i[in_ep_index])))
--------------1-------------- -----------------2-----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T4,T5,T6 |
LINE 159
EXPRESSION ((logic'((in_xact_state == StSendData))) & more_data_to_send)
-------------------1------------------- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T4,T5,T6 |
LINE 177
EXPRESSION (ep_active && in_token_received)
----1---- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T4,T5,T6 |
LINE 209
EXPRESSION (((!more_data_to_send)) || (((&in_ep_get_addr_o)) && tx_data_get_i))
-----------1---------- --------------------2-------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T21,T22 |
1 | 0 | Covered | T4,T5,T6 |
LINE 209
SUB-EXPRESSION (((&in_ep_get_addr_o)) && tx_data_get_i)
----------1---------- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T21,T22,T23 |
1 | 1 | Covered | T21,T22 |
LINE 239
EXPRESSION (timeout_cntdown_q == '0)
------------1------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Not Covered | |
LINE 291
EXPRESSION (link_reset_i || ((!link_active_i)))
------1----- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 304
EXPRESSION (in_xact_state == StIdle)
------------1------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T1,T2,T3 |
LINE 306
EXPRESSION ((in_xact_state == StSendData) && tx_data_get_i)
--------------1-------------- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T4,T5,T6 |
LINE 306
SUB-EXPRESSION (in_xact_state == StSendData)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 330
EXPRESSION (setup_token_received && ep_active)
----------1--------- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T3,T7,T9 |
1 | 1 | Not Covered | |
LINE 332
EXPRESSION ((in_xact_state == StWaitAck) && ack_received)
--------------1------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T4,T5,T6 |
LINE 332
SUB-EXPRESSION (in_xact_state == StWaitAck)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T5,T6 |
LINE 358
EXPRESSION ((in_xact_state == StSendData) && tx_data_get_i)
--------------1-------------- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T4,T5,T6 |
LINE 358
SUB-EXPRESSION (in_xact_state == StSendData)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T5,T6 |
FSM Coverage for Module :
usb_fs_nb_in_pe
Summary for FSM :: in_xact_state
| Total | Covered | Percent | |
States |
6 |
6 |
100.00 |
(Not included in score) |
Transitions |
12 |
6 |
50.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: in_xact_state
states | Line No. | Covered | Tests |
StIdle |
292 |
Covered |
T1,T2,T3 |
StRcvdIn |
178 |
Covered |
T4,T5,T6 |
StSendData |
193 |
Covered |
T4,T5,T6 |
StWaitAck |
238 |
Covered |
T4,T5,T6 |
StWaitAckStart |
215 |
Covered |
T4,T5,T6 |
StWaitTxEnd |
217 |
Covered |
T4,T5,T6 |
transitions | Line No. | Covered | Tests |
StIdle->StRcvdIn |
178 |
Covered |
T4,T5,T6 |
StRcvdIn->StIdle |
292 |
Not Covered |
|
StRcvdIn->StSendData |
193 |
Covered |
T4,T5,T6 |
StSendData->StIdle |
292 |
Not Covered |
|
StSendData->StWaitAckStart |
215 |
Not Covered |
|
StSendData->StWaitTxEnd |
217 |
Covered |
T4,T5,T6 |
StWaitAck->StIdle |
292 |
Covered |
T4,T5,T6 |
StWaitAck->StRcvdIn |
252 |
Not Covered |
|
StWaitAckStart->StIdle |
292 |
Not Covered |
|
StWaitAckStart->StWaitAck |
238 |
Covered |
T4,T5,T6 |
StWaitTxEnd->StIdle |
292 |
Not Covered |
|
StWaitTxEnd->StWaitAckStart |
227 |
Covered |
T4,T5,T6 |
Branch Coverage for Module :
usb_fs_nb_in_pe
| Line No. | Total | Covered | Percent |
Branches |
|
47 |
35 |
74.47 |
TERNARY |
143 |
2 |
1 |
50.00 |
CASE |
175 |
20 |
11 |
55.00 |
IF |
271 |
2 |
2 |
100.00 |
IF |
279 |
2 |
2 |
100.00 |
IF |
288 |
3 |
3 |
100.00 |
IF |
301 |
4 |
4 |
100.00 |
IF |
313 |
3 |
3 |
100.00 |
IF |
330 |
3 |
2 |
66.67 |
IF |
336 |
2 |
1 |
50.00 |
IF |
345 |
3 |
3 |
100.00 |
IF |
355 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_in_pe.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_in_pe.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 143 (ep_in_hw) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 175 case (in_xact_state)
-2-: 177 if ((ep_active && in_token_received))
-3-: 188 if (in_ep_iso_i[in_ep_index])
-4-: 195 if (in_ep_stall_i[in_ep_index])
-5-: 198 if (in_ep_has_data_i[in_ep_index])
-6-: 209 if (((!more_data_to_send) || ((&in_ep_get_addr_o) && tx_data_get_i)))
-7-: 210 if (in_ep_iso_i[in_ep_index])
-8-: 214 if (tx_pkt_end_i)
-9-: 226 if (tx_pkt_end_i)
-10-: 237 if (rx_pkt_start_i)
-11-: 239 if ((timeout_cntdown_q == '0))
-12-: 248 if (ack_received)
-13-: 251 if (in_token_received)
-14-: 254 if (rx_pkt_end_i)
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | Status | Tests |
StIdle |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T4,T5,T6 |
StIdle |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StRcvdIn |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
StRcvdIn |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
StRcvdIn |
- |
0 |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T4,T5,T6 |
StRcvdIn |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
StSendData |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
StSendData |
- |
- |
- |
- |
1 |
0 |
1 |
- |
- |
- |
- |
- |
- |
Not Covered |
|
StSendData |
- |
- |
- |
- |
1 |
0 |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T4,T5,T6 |
StSendData |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T4,T5,T6 |
StWaitTxEnd |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T4,T5,T6 |
StWaitTxEnd |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
Covered |
T4,T5,T6 |
StWaitAckStart |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
Covered |
T4,T5,T6 |
StWaitAckStart |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
Not Covered |
|
StWaitAckStart |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
Covered |
T4,T5,T6 |
StWaitAck |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T4,T5,T6 |
StWaitAck |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
Not Covered |
|
StWaitAck |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
1 |
Not Covered |
|
StWaitAck |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
LineNo. Expression
-1-: 271 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 279 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 288 if ((!rst_ni))
-2-: 291 if ((link_reset_i || (!link_active_i)))
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 301 if ((!rst_ni))
-2-: 304 if ((in_xact_state == StIdle))
-3-: 306 if (((in_xact_state == StSendData) && tx_data_get_i))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 313 if ((!rst_ni))
-2-: 317 if (in_token_received)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 330 if ((setup_token_received && ep_active))
-2-: 332 if (((in_xact_state == StWaitAck) && ack_received))
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Not Covered |
|
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 336 if (in_datatog_we_i)
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 345 if ((!rst_ni))
-2-: 347 if (link_reset_i)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 355 if ((!rst_ni))
-2-: 358 if (((in_xact_state == StSendData) && tx_data_get_i))
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
usb_fs_nb_in_pe
Assertion Details
InXactStateValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114481951 |
114425631 |
0 |
0 |
T1 |
402707 |
402548 |
0 |
0 |
T2 |
403470 |
403291 |
0 |
0 |
T3 |
401610 |
401455 |
0 |
0 |
T4 |
404958 |
404782 |
0 |
0 |
T5 |
402645 |
402503 |
0 |
0 |
T6 |
405548 |
405386 |
0 |
0 |
T7 |
401777 |
401520 |
0 |
0 |
T8 |
402181 |
401975 |
0 |
0 |
T9 |
401744 |
401554 |
0 |
0 |
T10 |
403731 |
403578 |
0 |
0 |