Module Definition
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Module : tlul_adapter_sram
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.16 95.38 69.91 83.33 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_no_stubbed_memory.u_tlul2sram 87.16 95.38 69.91 83.33 100.00



Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.16 95.38 69.91 83.33 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.66 85.71 70.51 78.41 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
87.49 96.38 62.63 93.46 85.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_err 66.91 76.92 65.71 25.00 100.00
u_reqfifo 87.85 95.00 73.08 83.33 100.00
u_rsp_gen 91.67 83.33 100.00
u_rspfifo 89.12 95.00 76.47 85.00 100.00
u_sram_byte 100.00 100.00
u_sramreqfifo 86.89 95.00 69.23 83.33 100.00
u_tlul_data_integ_enc_data 0.00 0.00
u_tlul_data_integ_enc_instr 0.00 0.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : tlul_adapter_sram
Line No.TotalCoveredPercent
TOTAL656295.38
ALWAYS9333100.00
CONT_ASSIGN10211100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN11411100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22311100.00
CONT_ASSIGN22411100.00
ALWAYS2298675.00
ALWAYS2496583.33
CONT_ASSIGN26311100.00
CONT_ASSIGN26711100.00
CONT_ASSIGN28611100.00
CONT_ASSIGN29111100.00
CONT_ASSIGN29711100.00
CONT_ASSIGN30111100.00
CONT_ASSIGN32111100.00
CONT_ASSIGN32211100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32411100.00
ALWAYS35466100.00
ALWAYS36655100.00
CONT_ASSIGN38111100.00
CONT_ASSIGN38211100.00
CONT_ASSIGN38311100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN38811100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39811100.00
CONT_ASSIGN40111100.00
CONT_ASSIGN40511100.00
CONT_ASSIGN40611100.00
CONT_ASSIGN40811100.00
CONT_ASSIGN41511100.00
ALWAYS43333100.00
CONT_ASSIGN43911100.00
CONT_ASSIGN44211100.00
CONT_ASSIGN44711100.00
CONT_ASSIGN45200
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
94 1 1
95 1 1
96 unreachable
MISSING_ELSE
102 1 1
107 1 1
114 1 1
139 1 1
151 1 1
222 1 1
223 1 1
224 1 1
229 1 1
231 1 1
232 1 1
234 0 1
235 1 1
236 1 1
239 0 1
242 1 1
249 1 1
251 1 1
252 1 1
253 1 1
255 0 1
258 1 1
263 1 1
267 1 1
286 1 1
291 1 1
297 1 1
301 1 1
321 1 1
322 1 1
323 1 1
324 1 1
354 1 1
355 1 1
357 1 1
358 1 1
359 1 1
360 1 1
MISSING_ELSE
366 1 1
367 1 1
369 1 1
370 1 1
371 1 1
MISSING_ELSE
381 1 1
382 1 1
383 1 1
387 1 1
388 1 1
390 1 1
391 1 1
398 1 1
401 1 1
405 1 1
406 1 1
408 1 1
415 1 1
433 1 1
434 1 1
435 1 1
439 1 1
442 1 1
447 1 1
452 unreachable


Cond Coverage for Module : tlul_adapter_sram
TotalCoveredPercent
Conditions1137969.91
Logical1137969.91
Non-Logical00
Event00

 LINE       95
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       102
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010Unreachable
100Unreachable

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T27,T12
10CoveredT1,T2,T4

 LINE       107
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       139
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT8,T27,T28
000001Unreachable
000010CoveredT1,T2,T3
000100Not Covered
001000Unreachable
010000Unreachable
100000Not Covered

 LINE       222
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT8,T27,T28
11CoveredT8,T27,T28

 LINE       223
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT27,T29,T30
11CoveredT8,T27,T28

 LINE       224
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT8,T27,T28

 LINE       235
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0Not Covered
1CoveredT8,T27,T28

 LINE       252
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0Not Covered
1CoveredT8,T27,T28

 LINE       253
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00CoveredT8,T27,T28
01Not Covered
10Not Covered

 LINE       263
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101Not Covered
1110Not Covered
1111CoveredT8,T27,T28

 LINE       263
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T27,T28

 LINE       291
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T27,T28

 LINE       291
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT8,T27,T28

 LINE       297
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01Not Covered
10CoveredT8,T27,T28
11Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T27,T28

 LINE       301
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       301
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT8,T27,T28
11Not Covered

 LINE       301
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T27,T28

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T27,T28

 LINE       301
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT8,T27,T28
11Not Covered

 LINE       301
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------
-1--2--3-StatusTests
011Not Covered
101CoveredT30,T31,T32
110Not Covered
111CoveredT1,T2,T3

 LINE       301
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------
-1--2-StatusTests
00Not Covered
01CoveredT1,T2,T4
10CoveredT8,T27,T28

 LINE       321
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT8,T27,T28
110Not Covered
111CoveredT8,T27,T28

 LINE       323
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT8,T27,T28
11Not Covered

 LINE       324
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T27,T28

 LINE       360
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT8,T27,T28
1Not Covered

 LINE       360
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10CoveredT8,T27,T28
11Not Covered

 LINE       383
 EXPRESSION (((|wmask_intg)) & ((|wdata_intg)))
             -------1-------   -------2-------
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT8,T27,T28

 LINE       391
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       391
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       405
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT8,T27,T28

 LINE       408
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT30,T31,T32
10Not Covered
11CoveredT8,T27,T28

 LINE       447
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T27,T28

 LINE       447
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT8,T27,T28

 LINE       447
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T27,T28

Branch Coverage for Module : tlul_adapter_sram
Line No.TotalCoveredPercent
Branches 24 20 83.33
TERNARY 107 2 2 100.00
TERNARY 291 2 2 100.00
TERNARY 297 3 2 66.67
TERNARY 324 2 2 100.00
TERNARY 447 2 2 100.00
IF 93 2 2 100.00
IF 231 4 2 50.00
IF 251 3 2 66.67
IF 357 2 2 100.00
IF 369 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 107 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 291 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Covered T8,T27,T28
0 Covered T1,T2,T3


LineNo. Expression -1-: 297 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 297 (vld_rd_rsp) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T8,T27,T28
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 324 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T8,T27,T28
0 Covered T1,T2,T3


LineNo. Expression -1-: 447 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Covered T8,T27,T28
0 Covered T1,T2,T3


LineNo. Expression -1-: 93 if ((!rst_ni)) -2-: 95 if ((intg_error || rsp_fifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Unreachable
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 231 if (reqfifo_rvalid) -2-: 232 if (reqfifo_rdata.error) -3-: 235 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Not Covered
1 0 1 Covered T8,T27,T28
1 0 0 Not Covered
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 251 if (reqfifo_rvalid) -2-: 252 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T8,T27,T28
1 0 Not Covered
0 - Covered T1,T2,T3


LineNo. Expression -1-: 357 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T8,T27,T28
0 Covered T1,T2,T3


LineNo. Expression -1-: 369 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T8,T27,T28
0 Covered T1,T2,T3


Assert Coverage for Module : tlul_adapter_sram
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 14 14 100.00 14 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 14 14 100.00 14 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 114481951 114425631 0 0
DataIntgOptions_A 289 289 0 0
ReqOutKnown_A 114481951 114425631 0 0
SramDwHasByteGranularity_A 289 289 0 0
SramDwIsMultipleOfTlulWidth_A 289 289 0 0
TlOutKnown_A 114481951 114425631 0 0
TlOutPayloadKnown_A 114481951 161 0 0
TlOutPayloadKnown_AKnownEnable 114481951 114425631 0 0
WdataOutKnown_A 114481951 114425631 0 0
WeOutKnown_A 114481951 114425631 0 0
WmaskOutKnown_A 114481951 114425631 0 0
adapterNoReadOrWrite 289 289 0 0
rvalidHighReqFifoEmpty 114481951 98 0 0
rvalidHighWhenRspFifoFull 114481951 98 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 114481951 114425631 0 0
T1 402707 402548 0 0
T2 403470 403291 0 0
T3 401610 401455 0 0
T4 404958 404782 0 0
T5 402645 402503 0 0
T6 405548 405386 0 0
T7 401777 401520 0 0
T8 402181 401975 0 0
T9 401744 401554 0 0
T10 403731 403578 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 289 289 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 114481951 114425631 0 0
T1 402707 402548 0 0
T2 403470 403291 0 0
T3 401610 401455 0 0
T4 404958 404782 0 0
T5 402645 402503 0 0
T6 405548 405386 0 0
T7 401777 401520 0 0
T8 402181 401975 0 0
T9 401744 401554 0 0
T10 403731 403578 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 289 289 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 289 289 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

TlOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 114481951 114425631 0 0
T1 402707 402548 0 0
T2 403470 403291 0 0
T3 401610 401455 0 0
T4 404958 404782 0 0
T5 402645 402503 0 0
T6 405548 405386 0 0
T7 401777 401520 0 0
T8 402181 401975 0 0
T9 401744 401554 0 0
T10 403731 403578 0 0

TlOutPayloadKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 114481951 161 0 0
T8 402181 2 0 0
T9 401744 0 0 0
T10 403731 0 0 0
T11 404695 0 0 0
T12 404076 0 0 0
T13 403483 0 0 0
T14 402501 0 0 0
T17 401187 0 0 0
T27 401654 2 0 0
T28 401592 2 0 0
T29 0 2 0 0
T30 0 7 0 0
T33 0 2 0 0
T34 0 2 0 0
T35 0 2 0 0
T36 0 2 0 0
T37 0 2 0 0

TlOutPayloadKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 114481951 114425631 0 0
T1 402707 402548 0 0
T2 403470 403291 0 0
T3 401610 401455 0 0
T4 404958 404782 0 0
T5 402645 402503 0 0
T6 405548 405386 0 0
T7 401777 401520 0 0
T8 402181 401975 0 0
T9 401744 401554 0 0
T10 403731 403578 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 114481951 114425631 0 0
T1 402707 402548 0 0
T2 403470 403291 0 0
T3 401610 401455 0 0
T4 404958 404782 0 0
T5 402645 402503 0 0
T6 405548 405386 0 0
T7 401777 401520 0 0
T8 402181 401975 0 0
T9 401744 401554 0 0
T10 403731 403578 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 114481951 114425631 0 0
T1 402707 402548 0 0
T2 403470 403291 0 0
T3 401610 401455 0 0
T4 404958 404782 0 0
T5 402645 402503 0 0
T6 405548 405386 0 0
T7 401777 401520 0 0
T8 402181 401975 0 0
T9 401744 401554 0 0
T10 403731 403578 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 114481951 114425631 0 0
T1 402707 402548 0 0
T2 403470 403291 0 0
T3 401610 401455 0 0
T4 404958 404782 0 0
T5 402645 402503 0 0
T6 405548 405386 0 0
T7 401777 401520 0 0
T8 402181 401975 0 0
T9 401744 401554 0 0
T10 403731 403578 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 289 289 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 114481951 98 0 0
T8 402181 2 0 0
T9 401744 0 0 0
T10 403731 0 0 0
T11 404695 0 0 0
T12 404076 0 0 0
T13 403483 0 0 0
T14 402501 0 0 0
T17 401187 0 0 0
T27 401654 2 0 0
T28 401592 2 0 0
T29 0 2 0 0
T30 0 2 0 0
T33 0 2 0 0
T34 0 2 0 0
T35 0 2 0 0
T36 0 2 0 0
T37 0 2 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 114481951 98 0 0
T8 402181 2 0 0
T9 401744 0 0 0
T10 403731 0 0 0
T11 404695 0 0 0
T12 404076 0 0 0
T13 403483 0 0 0
T14 402501 0 0 0
T17 401187 0 0 0
T27 401654 2 0 0
T28 401592 2 0 0
T29 0 2 0 0
T30 0 2 0 0
T33 0 2 0 0
T34 0 2 0 0
T35 0 2 0 0
T36 0 2 0 0
T37 0 2 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%