Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.67	96.45	63.89	92.99		85.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	111929576	12517	0	0
ep_in_enable_rd_A	111929576	1569	0	0
ep_out_enable_rd_A	111929576	1474	0	0
in_iso_rd_A	111929576	1882	0	0
intr_enable_rd_A	111929576	2029	0	0
out_iso_rd_A	111929576	1465	0	0
phy_config_rd_A	111929576	1066	0	0
phy_pins_drive_rd_A	111929576	1591	0	0
rxenable_setup_rd_A	111929576	1750	0	0
set_nak_out_rd_A	111929576	1550	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111929576	12517	0	0
T35	16083	771	0	0
T36	6864	4	0	0
T37	12722	2	0	0
T46	3888	23	0	0
T124	9157	980	0	0
T125	16432	969	0	0
T126	9594	807	0	0
T127	4762	876	0	0
T128	2593	445	0	0
T129	5780	12	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111929576	1569	0	0
T41	1877	7	0	0
T61	4402	48	0	0
T62	7632	23	0	0
T64	7689	75	0	0
T132	7461	19	0	0
T135	3212	20	0	0
T136	3672	38	0	0
T137	8161	28	0	0
T138	2294	19	0	0
T166	7653	116	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111929576	1474	0	0
T41	1877	2	0	0
T61	4402	41	0	0
T62	7632	61	0	0
T64	7689	27	0	0
T132	7461	33	0	0
T135	3212	10	0	0
T136	3672	81	0	0
T137	8161	79	0	0
T138	2294	6	0	0
T166	7653	56	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111929576	1882	0	0
T41	1877	9	0	0
T61	4402	21	0	0
T62	7632	33	0	0
T64	7689	84	0	0
T132	7461	66	0	0
T135	3212	5	0	0
T136	3672	51	0	0
T137	8161	31	0	0
T138	2294	18	0	0
T166	7653	116	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111929576	2029	0	0
T41	1877	1	0	0
T61	4402	48	0	0
T62	7632	31	0	0
T64	7689	36	0	0
T132	7461	37	0	0
T135	3212	53	0	0
T136	3672	13	0	0
T137	8161	47	0	0
T138	2294	8	0	0
T166	7653	11	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111929576	1465	0	0
T35	16083	10	0	0
T61	4402	9	0	0
T62	7632	30	0	0
T64	7689	16	0	0
T132	7461	44	0	0
T135	3212	67	0	0
T136	3672	62	0	0
T137	8161	27	0	0
T138	2294	33	0	0
T167	12740	6	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111929576	1066	0	0
T41	1877	4	0	0
T61	4402	24	0	0
T62	7632	40	0	0
T64	7689	34	0	0
T132	7461	35	0	0
T135	3212	1	0	0
T136	3672	19	0	0
T137	8161	71	0	0
T138	2294	5	0	0
T166	7653	44	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111929576	1591	0	0
T61	4402	9	0	0
T62	7632	63	0	0
T64	7689	51	0	0
T132	7461	52	0	0
T135	3212	28	0	0
T136	3672	31	0	0
T137	8161	49	0	0
T138	2294	8	0	0
T166	7653	54	0	0
T167	12740	1	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111929576	1750	0	0
T41	1877	2	0	0
T61	4402	22	0	0
T62	7632	12	0	0
T64	7689	57	0	0
T132	7461	24	0	0
T135	3212	35	0	0
T136	3672	60	0	0
T137	8161	16	0	0
T138	2294	27	0	0
T166	7653	103	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111929576	1550	0	0
T61	4402	33	0	0
T62	7632	2	0	0
T64	7689	29	0	0
T132	7461	49	0	0
T135	3212	4	0	0
T136	3672	82	0	0
T137	8161	52	0	0
T138	2294	10	0	0
T166	7653	52	0	0
T168	2153	56	0	0