Unified Coverage Report :: Module :: usbdev

Module : usbdev

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.67	96.45	63.89	92.99		85.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	87.67	96.45	63.89	92.99		85.00	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.67	96.45	63.89	92.99		85.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.03	95.94	86.92	96.73	45.31	93.92	97.36

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_event	100.00	100.00				100.00
gen_no_stubbed_memory.u_memory_1p	98.96	95.83	100.00			100.00	100.00
gen_no_stubbed_memory.u_tlul2sram	83.66	85.71	70.51			78.41	100.00
i_usbdev_iomux	66.67	88.89	44.44			83.33	50.00
intr_av_out_empty	81.39	90.00	55.56			80.00	100.00
intr_av_overflow	81.25	100.00	25.00			100.00	100.00
intr_av_setup_empty	81.39	90.00	55.56			80.00	100.00
intr_disconnected	89.58	100.00	58.33			100.00	100.00
intr_frame	81.25	100.00	25.00			100.00	100.00
intr_host_lost	81.25	100.00	25.00			100.00	100.00
intr_hw_pkt_received	86.94	90.00	77.78			80.00	100.00
intr_hw_pkt_sent	84.17	90.00	66.67			80.00	100.00
intr_link_in_err	81.25	100.00	25.00			100.00	100.00
intr_link_out_err	89.58	100.00	58.33			100.00	100.00
intr_link_reset	89.58	100.00	58.33			100.00	100.00
intr_link_resume	81.25	100.00	25.00			100.00	100.00
intr_link_suspend	81.25	100.00	25.00			100.00	100.00
intr_powered	89.58	100.00	58.33			100.00	100.00
intr_rx_bitstuff_err	81.25	100.00	25.00			100.00	100.00
intr_rx_crc_err	81.25	100.00	25.00			100.00	100.00
intr_rx_full	73.06	90.00	22.22			80.00	100.00
intr_rx_pid_err	81.25	100.00	25.00			100.00	100.00
tlul_assert_device	95.24	100.00				85.71	100.00
u_reg	95.59	97.90	95.24	100.00		97.72	87.10
usbdev_avoutfifo	89.34	97.62	70.83			88.89	100.00
usbdev_avsetupfifo	89.34	97.62	70.83			88.89	100.00
usbdev_csr_assert	100.00						100.00
usbdev_impl	80.45	91.16	82.13		45.31	83.65	100.00
usbdev_rxfifo	80.50	90.48	61.54			70.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : usbdev

	Line No.	Total	Covered	Percent
TOTAL		141	136	96.45
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
ALWAYS	211	5	5	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	252	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	255	1	1	100.00
CONT_ASSIGN	257	1	1	100.00
CONT_ASSIGN	305	1	1	100.00
CONT_ASSIGN	310	1	1	100.00
CONT_ASSIGN	313	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	341	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	343	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	345	1	1	100.00
CONT_ASSIGN	349	1	0	0.00
ALWAYS	372	0	0
ALWAYS	372	3	3	100.00
ALWAYS	380	0	0
ALWAYS	380	4	4	100.00
ALWAYS	389	0	0
ALWAYS	389	3	3	100.00
ALWAYS	396	0	0
ALWAYS	396	3	3	100.00
ALWAYS	403	0	0
ALWAYS	403	3	3	100.00
ALWAYS	410	0	0
ALWAYS	410	2	2	100.00
CONT_ASSIGN	417	1	0	0.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	426	1	0	0.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
ALWAYS	434	3	3	100.00
ALWAYS	441	0	0
ALWAYS	441	3	3	100.00
ALWAYS	450	3	3	100.00
ALWAYS	462	3	3	100.00
ALWAYS	469	0	0
ALWAYS	469	3	3	100.00
ALWAYS	476	10	10	100.00
ALWAYS	494	0	0
ALWAYS	494	3	3	100.00
ALWAYS	502	0	0
ALWAYS	502	3	3	100.00
CONT_ASSIGN	512	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	625	1	1	100.00
CONT_ASSIGN	626	1	1	100.00
CONT_ASSIGN	628	1	1	100.00
CONT_ASSIGN	629	1	1	100.00
CONT_ASSIGN	647	1	1	100.00
CONT_ASSIGN	650	1	1	100.00
ALWAYS	656	0	0
ALWAYS	656	8	8	100.00
CONT_ASSIGN	736	1	1	100.00
CONT_ASSIGN	737	1	1	100.00
CONT_ASSIGN	738	1	1	100.00
CONT_ASSIGN	739	1	1	100.00
CONT_ASSIGN	747	1	1	100.00
ALWAYS	756	8	8	100.00
CONT_ASSIGN	770	1	1	100.00
CONT_ASSIGN	771	0	0
CONT_ASSIGN	774	1	1	100.00
CONT_ASSIGN	775	1	1	100.00
CONT_ASSIGN	832	1	1	100.00
CONT_ASSIGN	833	1	1	100.00
CONT_ASSIGN	837	1	1	100.00
CONT_ASSIGN	1100	1	1	100.00
CONT_ASSIGN	1101	1	1	100.00
CONT_ASSIGN	1102	1	1	100.00
CONT_ASSIGN	1103	1	1	100.00
CONT_ASSIGN	1143	1	1	100.00
CONT_ASSIGN	1146	1	1	100.00
CONT_ASSIGN	1155	1	1	100.00
ALWAYS	1158	5	3	60.00
ALWAYS	1167	3	3	100.00
CONT_ASSIGN	1180	1	1	100.00
CONT_ASSIGN	1183	1	1	100.00
CONT_ASSIGN	1190	1	1	100.00
ALWAYS	1194	3	3	100.00
CONT_ASSIGN	1201	1	1	100.00
CONT_ASSIGN	1206	1	1	100.00
CONT_ASSIGN	1208	1	1	100.00
CONT_ASSIGN	1216	0	0
CONT_ASSIGN	1218	0	0
CONT_ASSIGN	1220	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
122	1	1
209	1	1
211	1	1
212	1	1
214	1	1
215	1	1
217	1	1
246	1	1
247	1	1
248	1	1
252	1	1
253	1	1
255	1	1
257	1	1
305	1	1
310	1	1
313	1	1
316	1	1
341	1	1
342	1	1
343	1	1
344	1	1
345	1	1
349	0	1
372	1	1
373	1	1
374	1	1
380	1	1
381	1	1
382	1	1
383	1	1
389	1	1
390	1	1
391	1	1
396	1	1
397	1	1
398	1	1
403	1	1
404	1	1
405	1	1
410	1	1
411	1	1
417	0	1
418	1	1
419	1	1
421	1	1
426	0	1
427	1	1
428	1	1
430	1	1
434	1	1
435	1	1
436	1	1
			MISSING_ELSE
441	1	1
442	1	1
443	1	1
450	1	1
451	1	1
452	1	1
462	1	1
463	1	1
464	1	1
			MISSING_ELSE
469	1	1
470	1	1
471	1	1
476	1	1
477	1	1
478	1	1
479	1	1
480	1	1
482	1	1
484	1	1
485	1	1
486	1	1
488	1	1
			MISSING_ELSE
494	1	1
495	1	1
496	1	1
502	1	1
503	1	1
504	1	1
512	1	1
513	1	1
514	1	1
625	1	1
626	1	1
628	1	1
629	1	1
647	1	1
650	1	1
656	1	1
657	1	1
658	1	1
659	1	1
660	1	1
661	1	1
663	1	1
664	1	1
736	1	1
737	1	1
738	1	1
739	1	1
747	1	1
756	1	1
757	1	1
758	1	1
759	1	1
761	1	1
762	1	1
764	1	1
765	1	1
			MISSING_ELSE
770	1	1
771		unreachable
774	1	1
775	1	1
832	1	1
833	1	1
837	1	1
1100	1	1
1101	1	1
1102	1	1
1103	1	1
1143	1	1
1146	1	1
1155	1	1
1158	1	1
1159	1	1
1160	0	1
1161	1	1
1162	0	1
			MISSING_ELSE
1167	1	1
1168	1	1
1170	1	1
1180	1	1
1183	1	1
1190	1	1
1194	1	1
1195	1	1
1197	1	1
1201	1	1
1206	1	1
1208	1	1
1216		unreachable
1218		unreachable
1220		unreachable

---

Cond Coverage for Module : usbdev

	Total	Covered	Percent
Conditions	108	69	63.89
Logical	108	69	63.89
Non-Logical	0	0
Event	0	0

 LINE       209
 EXPRESSION (ns_cnt == 6'd47)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       246
 EXPRESSION (reg2hw.fifo_ctrl.avsetup_rst.qe & reg2hw.fifo_ctrl.avsetup_rst.q)
             ---------------1---------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T20
1	0	Covered	T1,T19,T20
1	1	Covered	T1,T19,T20

 LINE       247
 EXPRESSION (reg2hw.fifo_ctrl.avout_rst.qe & reg2hw.fifo_ctrl.avout_rst.q)
             --------------1--------------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T20
1	0	Covered	T1,T19,T20
1	1	Covered	T1,T19,T20

 LINE       248
 EXPRESSION (reg2hw.fifo_ctrl.rx_rst.qe & reg2hw.fifo_ctrl.rx_rst.q)
             -------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T19,T20
1	1	Not Covered

 LINE       252
 EXPRESSION (connect_en & ((~avsetup_rvalid)))
             -----1----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T2,T3

 LINE       253
 EXPRESSION (connect_en & ((~avout_rvalid)))
             -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       255
 EXPRESSION ((reg2hw.avsetupbuffer.qe & ((~avsetup_fifo_wready))) | (reg2hw.avoutbuffer.qe & ((~avout_fifo_wready))))
             --------------------------1-------------------------   ------------------------2-----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       255
 SUB-EXPRESSION (reg2hw.avsetupbuffer.qe & ((~avsetup_fifo_wready)))
                 -----------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T7
1	1	Not Covered

 LINE       255
 SUB-EXPRESSION (reg2hw.avoutbuffer.qe & ((~avout_fifo_wready)))
                 ----------1----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       257
 EXPRESSION (connect_en & ((~rx_fifo_rvalid)))
             -----1----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       305
 EXPRESSION (reg2hw.rxfifo.ep.re | reg2hw.rxfifo.setup.re | reg2hw.rxfifo.size.re | reg2hw.rxfifo.buffer.re)
             ---------1---------   -----------2----------   ----------3----------   -----------4-----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Not Covered
1	0	0	0	Not Covered

 LINE       316
 EXPRESSION (rx_wready & (rx_depth < (RXFifoDepth - 1)))
             ----1----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       417
 EXPRESSION (reg2hw.out_data_toggle.status.qe & reg2hw.out_data_toggle.mask.qe)
             ----------------1---------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       426
 EXPRESSION (reg2hw.in_data_toggle.status.qe & reg2hw.in_data_toggle.mask.qe)
             ---------------1---------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       435
 EXPRESSION (in_ep_xact_end && in_endpoint_val)
             -------1------    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T3,T10,T13

 LINE       463
 EXPRESSION (rx_wvalid && out_endpoint_val)
             ----1----    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       482
 EXPRESSION (setup_received & out_endpoint_val)
             -------1------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T6,T7,T9

 LINE       486
 EXPRESSION (in_ep_xact_end & in_endpoint_val)
             -------1------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T3,T10,T13

 LINE       504
 EXPRESSION (reg2hw.configin[i].rdy.q | reg2hw.configin[i].pend.q)
             ------------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T3,T10,T13

 LINE       513
 EXPRESSION (cfg_pinflip ? 1'b0 : usb_pullup_en)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       514
 EXPRESSION (((!cfg_pinflip)) ? 1'b0 : usb_pullup_en)
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       629
 EXPRESSION (reg2hw.usbctrl.resume_link_active.qe & reg2hw.usbctrl.resume_link_active.q)
             ------------------1-----------------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       736
 EXPRESSION (usb_mem_b_req | sw_mem_a_req)
             ------1------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T8
1	0	Covered	T2,T3,T4

 LINE       737
 EXPRESSION (usb_mem_b_req ? usb_mem_b_write : sw_mem_a_write)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       738
 EXPRESSION (usb_mem_b_req ? usb_mem_b_addr : sw_mem_a_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       739
 EXPRESSION (usb_mem_b_req ? usb_mem_b_wdata : sw_mem_a_wdata)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       762
 EXPRESSION (usb_mem_b_req & ((!usb_mem_b_write)))
             ------1------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T10,T13

 LINE       770
 EXPRESSION (gen_no_stubbed_memory.mem_rvalid & ((!gen_no_stubbed_memory.mem_rsteering)))
             ----------------1---------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T10,T13
1	1	Covered	T2,T5,T8

 LINE       775
 EXPRESSION (gen_no_stubbed_memory.mem_b_read_q ? gen_no_stubbed_memory.mem_rdata : gen_no_stubbed_memory.mem_b_rdata_q)
             -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T10,T13

 LINE       837
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       1146
 EXPRESSION (use_diff_rcvr & ((~link_suspend)))
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       1155
 EXPRESSION (usb_rcvr_ok_counter_q == '0)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1159
 EXPRESSION (use_diff_rcvr & ((!usb_rx_enable_o)))
             ------1------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       1161
 EXPRESSION (us_tick && (usb_rcvr_ok_counter_q > '0))
             ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       1183
 EXPRESSION (usb_ref_disable ? 1'b0 : event_sof)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       1190
 EXPRESSION (usb_ref_pulse_o ? 1'b1 : ((((!link_active)) || host_lost || usb_ref_disable) ? 1'b0 : usb_ref_val_q))
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       1190
 SUB-EXPRESSION ((((!link_active)) || host_lost || usb_ref_disable) ? 1'b0 : usb_ref_val_q)
                 -------------------------1------------------------

-1-	Status	Tests
0	Covered	T2,T3,T18
1	Covered	T1,T2,T3

 LINE       1190
 SUB-EXPRESSION (((!link_active)) || host_lost || usb_ref_disable)
                 --------1-------    ----2----    -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T2,T3,T18
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Covered	T1,T2,T3

 LINE       1206
 EXPRESSION (reg2hw.wake_control.suspend_req.qe & reg2hw.wake_control.suspend_req.q)
             -----------------1----------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       1208
 EXPRESSION (reg2hw.wake_control.wake_ack.qe & reg2hw.wake_control.wake_ack.q)
             ---------------1---------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Toggle Coverage for Module : usbdev

	Total	Covered	Percent
Totals	68	59	86.76
Total Bits	428	398	92.99
Total Bits 0->1	214	199	92.99
Total Bits 1->0	214	199	92.99

Ports	68	59	86.76
Port Bits	428	398	92.99
Port Bits 0->1	214	199	92.99
Port Bits 1->0	214	199	92.99

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T18	Yes	T1,T2,T3	INPUT
clk_aon_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_aon_ni	Yes	Yes	T2,T3,T18	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T19,T8,T9	Yes	T19,T8,T9	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T7	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T19,T20	Yes	T1,T4,T19	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T18	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T38,T39,T40	Yes	T38,T39,T40	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T38,T39,T40	Yes	T38,T39,T40	OUTPUT
cio_usb_dp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_usb_dn_i	Yes	Yes	T1,T2,T3	Yes	T2,T3,T18	INPUT
usb_rx_d_i	No	No		No		INPUT
cio_usb_dp_o	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	OUTPUT
cio_usb_dp_en_o	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
cio_usb_dn_o	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
cio_usb_dn_en_o	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
usb_tx_se0_o	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
usb_tx_d_o	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	OUTPUT
cio_sense_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
usb_dp_pullup_o	Yes	Yes	T2,T3,T18	Yes	T1,T2,T3	OUTPUT
usb_dn_pullup_o	Yes	Yes	T41,T42,T43	Yes	T41,T42,T43	OUTPUT
usb_rx_enable_o	Yes	Yes	T44,T36,T45	Yes	T44,T36,T45	OUTPUT
usb_tx_use_d_se0_o	Yes	Yes	T36,T37,T46	Yes	T36,T45,T37	OUTPUT
usb_aon_suspend_req_o	Yes	Yes	T43,T47,T48	Yes	T43,T47,T48	OUTPUT
usb_aon_wake_ack_o	Yes	Yes	T36,T37,T46	Yes	T36,T37,T46	OUTPUT
usb_aon_bus_reset_i	Unreachable	Unreachable		Unreachable		INPUT
usb_aon_sense_lost_i	Unreachable	Unreachable		Unreachable		INPUT
usb_aon_wake_detect_active_i	Unreachable	Unreachable		Unreachable		INPUT
usb_ref_val_o	No	No		No		OUTPUT
usb_ref_pulse_o	No	No		No		OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
intr_pkt_received_o	Yes	Yes	T6,T7,T9	Yes	T6,T7,T9	OUTPUT
intr_pkt_sent_o	Yes	Yes	T3,T10,T13	Yes	T3,T10,T13	OUTPUT
intr_powered_o	Yes	Yes	T36,T37,T46	Yes	T36,T45,T37	OUTPUT
intr_disconnected_o	Yes	Yes	T36,T37,T46	Yes	T44,T36,T37	OUTPUT
intr_host_lost_o	Yes	Yes	T41,T47,T48	Yes	T41,T47,T48	OUTPUT
intr_link_reset_o	Yes	Yes	T41,T48	Yes	T41,T48	OUTPUT
intr_link_suspend_o	Yes	Yes	T41,T48	Yes	T41,T48	OUTPUT
intr_link_resume_o	Yes	Yes	T43,T48	Yes	T43,T48	OUTPUT
intr_av_out_empty_o	Yes	Yes	T42,T48	Yes	T42,T48	OUTPUT
intr_rx_full_o	Yes	Yes	T42	Yes	T42	OUTPUT
intr_av_overflow_o	Yes	Yes	T43	Yes	T43	OUTPUT
intr_link_in_err_o	Yes	Yes	T47	Yes	T47	OUTPUT
intr_link_out_err_o	Yes	Yes	T43	Yes	T43	OUTPUT
intr_rx_crc_err_o	Yes	Yes	T43,T48	Yes	T43,T48	OUTPUT
intr_rx_pid_err_o	No	No		No		OUTPUT
intr_rx_bitstuff_err_o	Yes	Yes	T42,T48	Yes	T42,T48	OUTPUT
intr_frame_o	No	No		No		OUTPUT
intr_av_setup_empty_o	Yes	Yes	T42,T43,T48	Yes	T42,T43,T48	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : usbdev

	Line No.	Total	Covered	Percent
Branches		40	34	85.00
TERNARY	513	2	1	50.00
TERNARY	514	2	1	50.00
TERNARY	1183	2	1	50.00
TERNARY	1190	3	2	66.67
TERNARY	737	2	2	100.00
TERNARY	738	2	2	100.00
TERNARY	739	2	2	100.00
TERNARY	775	2	2	100.00
IF	211	3	3	100.00
IF	435	2	2	100.00
IF	463	2	2	100.00
IF	478	4	4	100.00
IF	659	2	2	100.00
IF	1159	3	1	33.33
IF	1167	2	2	100.00
IF	1194	2	2	100.00
IF	756	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	513	(cfg_pinflip) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	514	((!cfg_pinflip)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	1183	(usb_ref_disable) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1190	(usb_ref_pulse_o) ? 
-2-:	1190	((((!link_active) || host_lost) || usb_ref_disable)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Covered	T2,T3,T18

	LineNo.	Expression
-1-:	737	(usb_mem_b_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	738	(usb_mem_b_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	739	(usb_mem_b_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	775	(gen_no_stubbed_memory.mem_b_read_q) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	211	if ((!rst_n))
-2-:	214	if (us_tick)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	435	if ((in_ep_xact_end && in_endpoint_val))

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	463	if ((rx_wvalid && out_endpoint_val))

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	478	if (event_link_reset)
-2-:	482	if ((setup_received & out_endpoint_val))
-3-:	486	if ((in_ep_xact_end & in_endpoint_val))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T6,T7,T9
0	0	1	Covered	T3,T10,T13
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	659	if (((setup_received && out_endpoint_val) && (out_endpoint == 4'((unsigned'(i))))))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1159	if ((use_diff_rcvr & (!usb_rx_enable_o)))
-2-:	1161	if ((us_tick && (usb_rcvr_ok_counter_q > '0)))

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1167	if ((!rst_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1194	if ((!rst_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	756	if ((!rst_ni))
-2-:	764	if (gen_no_stubbed_memory.mem_b_read_q)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T10,T13
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : usbdev

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	35	35	100.00	35	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	35	35	100.00	35	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertsKnown_A	111207259	111152621	0	0
CIODnEnKnown_A	111207259	111152621	0	0
CIODnKnown_A	111207259	111152621	0	0
CIODpEnKnown_A	111207259	111152621	0	0
CIODpKnown_A	111207259	111152621	0	0
FpvSecCmRegWeOnehotCheck_A	111207259	30	0	0
TlOAReadyKnown_A	111207259	111152621	0	0
TlODValidKnown_A	111207259	111152621	0	0
USBAonSuspendReqKnown_A	111207259	111152621	0	0
USBAonWakeAckKnown_A	111207259	111152621	0	0
USBDnPUKnown_A	111207259	111152621	0	0
USBDpPUKnown_A	111207259	111152621	0	0
USBIntrAvOutEmptyKnown_A	111207259	111152621	0	0
USBIntrAvOverKnown_A	111207259	111152621	0	0
USBIntrAvSetupEmptyKnown_A	111207259	111152621	0	0
USBIntrDisConKnown_A	111207259	111152621	0	0
USBIntrFrameKnown_A	111207259	111152621	0	0
USBIntrHostLostKnown_A	111207259	111152621	0	0
USBIntrLinkInErrKnown_A	111207259	111152621	0	0
USBIntrLinkOutErrKnown_A	111207259	111152621	0	0
USBIntrLinkResKnown_A	111207259	111152621	0	0
USBIntrLinkRstKnown_A	111207259	111152621	0	0
USBIntrLinkSusKnown_A	111207259	111152621	0	0
USBIntrPktRcvdKnown_A	111207259	111152621	0	0
USBIntrPktSentKnown_A	111207259	111152621	0	0
USBIntrPwrdKnown_A	111207259	111152621	0	0
USBIntrRxBitstuffErrKnown_A	111207259	111152621	0	0
USBIntrRxCrCErrKnown_A	111207259	111152621	0	0
USBIntrRxFullKnown_A	111207259	111152621	0	0
USBIntrRxPidErrKnown_A	111207259	111152621	0	0
USBRefPulseKnown_A	111207259	111152621	0	0
USBRefValKnown_A	111207259	111152621	0	0
USBRxEnableKnown_A	111207259	111152621	0	0
USBTxDKnown_A	111207259	111152621	0	0
USBTxSe0Known_A	111207259	111152621	0	0

AlertsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111207259	111152621	0	0
T1	7265	7173	0	0
T2	402081	401888	0	0
T3	403381	403238	0	0
T4	404332	404179	0	0
T5	401570	401308	0	0
T6	406098	405861	0	0
T7	401957	401736	0	0
T18	401209	401092	0	0
T19	7538	7487	0	0
T20	12815	12720	0	0

CIODnEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111207259	111152621	0	0
T1	7265	7173	0	0
T2	402081	401888	0	0
T3	403381	403238	0	0
T4	404332	404179	0	0
T5	401570	401308	0	0
T6	406098	405861	0	0
T7	401957	401736	0	0
T18	401209	401092	0	0
T19	7538	7487	0	0
T20	12815	12720	0	0

CIODnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111207259	111152621	0	0
T1	7265	7173	0	0
T2	402081	401888	0	0
T3	403381	403238	0	0
T4	404332	404179	0	0
T5	401570	401308	0	0
T6	406098	405861	0	0
T7	401957	401736	0	0
T18	401209	401092	0	0
T19	7538	7487	0	0
T20	12815	12720	0	0

CIODpEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111207259	111152621	0	0
T1	7265	7173	0	0
T2	402081	401888	0	0
T3	403381	403238	0	0
T4	404332	404179	0	0
T5	401570	401308	0	0
T6	406098	405861	0	0
T7	401957	401736	0	0
T18	401209	401092	0	0
T19	7538	7487	0	0
T20	12815	12720	0	0

CIODpKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111207259	111152621	0	0
T1	7265	7173	0	0
T2	402081	401888	0	0
T3	403381	403238	0	0
T4	404332	404179	0	0
T5	401570	401308	0	0
T6	406098	405861	0	0
T7	401957	401736	0	0
T18	401209	401092	0	0
T19	7538	7487	0	0
T20	12815	12720	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111207259	30	0	0
T38	6961	10	0	0
T39	0	10	0	0
T40	0	10	0	0
T49	404224	0	0	0
T50	401741	0	0	0
T51	402652	0	0	0
T52	403280	0	0	0
T53	401399	0	0	0
T54	401201	0	0	0
T55	3100	0	0	0
T56	401776	0	0	0
T57	401768	0	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111207259	111152621	0	0
T1	7265	7173	0	0
T2	402081	401888	0	0
T3	403381	403238	0	0
T4	404332	404179	0	0
T5	401570	401308	0	0
T6	406098	405861	0	0
T7	401957	401736	0	0
T18	401209	401092	0	0
T19	7538	7487	0	0
T20	12815	12720	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111207259	111152621	0	0
T1	7265	7173	0	0
T2	402081	401888	0	0
T3	403381	403238	0	0
T4	404332	404179	0	0
T5	401570	401308	0	0
T6	406098	405861	0	0
T7	401957	401736	0	0
T18	401209	401092	0	0
T19	7538	7487	0	0
T20	12815	12720	0	0

USBAonSuspendReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111207259	111152621	0	0
T1	7265	7173	0	0
T2	402081	401888	0	0
T3	403381	403238	0	0
T4	404332	404179	0	0
T5	401570	401308	0	0
T6	406098	405861	0	0
T7	401957	401736	0	0
T18	401209	401092	0	0
T19	7538	7487	0	0
T20	12815	12720	0	0

USBAonWakeAckKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111207259	111152621	0	0
T1	7265	7173	0	0
T2	402081	401888	0	0
T3	403381	403238	0	0
T4	404332	404179	0	0
T5	401570	401308	0	0
T6	406098	405861	0	0
T7	401957	401736	0	0
T18	401209	401092	0	0
T19	7538	7487	0	0
T20	12815	12720	0	0

USBDnPUKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111207259	111152621	0	0
T1	7265	7173	0	0
T2	402081	401888	0	0
T3	403381	403238	0	0
T4	404332	404179	0	0
T5	401570	401308	0	0
T6	406098	405861	0	0
T7	401957	401736	0	0
T18	401209	401092	0	0
T19	7538	7487	0	0
T20	12815	12720	0	0

USBDpPUKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111207259	111152621	0	0
T1	7265	7173	0	0
T2	402081	401888	0	0
T3	403381	403238	0	0
T4	404332	404179	0	0
T5	401570	401308	0	0
T6	406098	405861	0	0
T7	401957	401736	0	0
T18	401209	401092	0	0
T19	7538	7487	0	0
T20	12815	12720	0	0

USBIntrAvOutEmptyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111207259	111152621	0	0
T1	7265	7173	0	0
T2	402081	401888	0	0
T3	403381	403238	0	0
T4	404332	404179	0	0
T5	401570	401308	0	0
T6	406098	405861	0	0
T7	401957	401736	0	0
T18	401209	401092	0	0
T19	7538	7487	0	0
T20	12815	12720	0	0

USBIntrAvOverKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111207259	111152621	0	0
T1	7265	7173	0	0
T2	402081	401888	0	0
T3	403381	403238	0	0
T4	404332	404179	0	0
T5	401570	401308	0	0
T6	406098	405861	0	0
T7	401957	401736	0	0
T18	401209	401092	0	0
T19	7538	7487	0	0
T20	12815	12720	0	0

USBIntrAvSetupEmptyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111207259	111152621	0	0
T1	7265	7173	0	0
T2	402081	401888	0	0
T3	403381	403238	0	0
T4	404332	404179	0	0
T5	401570	401308	0	0
T6	406098	405861	0	0
T7	401957	401736	0	0
T18	401209	401092	0	0
T19	7538	7487	0	0
T20	12815	12720	0	0

USBIntrDisConKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111207259	111152621	0	0
T1	7265	7173	0	0
T2	402081	401888	0	0
T3	403381	403238	0	0
T4	404332	404179	0	0
T5	401570	401308	0	0
T6	406098	405861	0	0
T7	401957	401736	0	0
T18	401209	401092	0	0
T19	7538	7487	0	0
T20	12815	12720	0	0

USBIntrFrameKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111207259	111152621	0	0
T1	7265	7173	0	0
T2	402081	401888	0	0
T3	403381	403238	0	0
T4	404332	404179	0	0
T5	401570	401308	0	0
T6	406098	405861	0	0
T7	401957	401736	0	0
T18	401209	401092	0	0
T19	7538	7487	0	0
T20	12815	12720	0	0

USBIntrHostLostKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111207259	111152621	0	0
T1	7265	7173	0	0
T2	402081	401888	0	0
T3	403381	403238	0	0
T4	404332	404179	0	0
T5	401570	401308	0	0
T6	406098	405861	0	0
T7	401957	401736	0	0
T18	401209	401092	0	0
T19	7538	7487	0	0
T20	12815	12720	0	0

USBIntrLinkInErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111207259	111152621	0	0
T1	7265	7173	0	0
T2	402081	401888	0	0
T3	403381	403238	0	0
T4	404332	404179	0	0
T5	401570	401308	0	0
T6	406098	405861	0	0
T7	401957	401736	0	0
T18	401209	401092	0	0
T19	7538	7487	0	0
T20	12815	12720	0	0

USBIntrLinkOutErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111207259	111152621	0	0
T1	7265	7173	0	0
T2	402081	401888	0	0
T3	403381	403238	0	0
T4	404332	404179	0	0
T5	401570	401308	0	0
T6	406098	405861	0	0
T7	401957	401736	0	0
T18	401209	401092	0	0
T19	7538	7487	0	0
T20	12815	12720	0	0

USBIntrLinkResKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111207259	111152621	0	0
T1	7265	7173	0	0
T2	402081	401888	0	0
T3	403381	403238	0	0
T4	404332	404179	0	0
T5	401570	401308	0	0
T6	406098	405861	0	0
T7	401957	401736	0	0
T18	401209	401092	0	0
T19	7538	7487	0	0
T20	12815	12720	0	0

USBIntrLinkRstKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111207259	111152621	0	0
T1	7265	7173	0	0
T2	402081	401888	0	0
T3	403381	403238	0	0
T4	404332	404179	0	0
T5	401570	401308	0	0
T6	406098	405861	0	0
T7	401957	401736	0	0
T18	401209	401092	0	0
T19	7538	7487	0	0
T20	12815	12720	0	0

USBIntrLinkSusKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111207259	111152621	0	0
T1	7265	7173	0	0
T2	402081	401888	0	0
T3	403381	403238	0	0
T4	404332	404179	0	0
T5	401570	401308	0	0
T6	406098	405861	0	0
T7	401957	401736	0	0
T18	401209	401092	0	0
T19	7538	7487	0	0
T20	12815	12720	0	0

USBIntrPktRcvdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111207259	111152621	0	0
T1	7265	7173	0	0
T2	402081	401888	0	0
T3	403381	403238	0	0
T4	404332	404179	0	0
T5	401570	401308	0	0
T6	406098	405861	0	0
T7	401957	401736	0	0
T18	401209	401092	0	0
T19	7538	7487	0	0
T20	12815	12720	0	0

USBIntrPktSentKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111207259	111152621	0	0
T1	7265	7173	0	0
T2	402081	401888	0	0
T3	403381	403238	0	0
T4	404332	404179	0	0
T5	401570	401308	0	0
T6	406098	405861	0	0
T7	401957	401736	0	0
T18	401209	401092	0	0
T19	7538	7487	0	0
T20	12815	12720	0	0

USBIntrPwrdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111207259	111152621	0	0
T1	7265	7173	0	0
T2	402081	401888	0	0
T3	403381	403238	0	0
T4	404332	404179	0	0
T5	401570	401308	0	0
T6	406098	405861	0	0
T7	401957	401736	0	0
T18	401209	401092	0	0
T19	7538	7487	0	0
T20	12815	12720	0	0

USBIntrRxBitstuffErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111207259	111152621	0	0
T1	7265	7173	0	0
T2	402081	401888	0	0
T3	403381	403238	0	0
T4	404332	404179	0	0
T5	401570	401308	0	0
T6	406098	405861	0	0
T7	401957	401736	0	0
T18	401209	401092	0	0
T19	7538	7487	0	0
T20	12815	12720	0	0

USBIntrRxCrCErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111207259	111152621	0	0
T1	7265	7173	0	0
T2	402081	401888	0	0
T3	403381	403238	0	0
T4	404332	404179	0	0
T5	401570	401308	0	0
T6	406098	405861	0	0
T7	401957	401736	0	0
T18	401209	401092	0	0
T19	7538	7487	0	0
T20	12815	12720	0	0

USBIntrRxFullKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111207259	111152621	0	0
T1	7265	7173	0	0
T2	402081	401888	0	0
T3	403381	403238	0	0
T4	404332	404179	0	0
T5	401570	401308	0	0
T6	406098	405861	0	0
T7	401957	401736	0	0
T18	401209	401092	0	0
T19	7538	7487	0	0
T20	12815	12720	0	0

USBIntrRxPidErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111207259	111152621	0	0
T1	7265	7173	0	0
T2	402081	401888	0	0
T3	403381	403238	0	0
T4	404332	404179	0	0
T5	401570	401308	0	0
T6	406098	405861	0	0
T7	401957	401736	0	0
T18	401209	401092	0	0
T19	7538	7487	0	0
T20	12815	12720	0	0

USBRefPulseKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111207259	111152621	0	0
T1	7265	7173	0	0
T2	402081	401888	0	0
T3	403381	403238	0	0
T4	404332	404179	0	0
T5	401570	401308	0	0
T6	406098	405861	0	0
T7	401957	401736	0	0
T18	401209	401092	0	0
T19	7538	7487	0	0
T20	12815	12720	0	0

USBRefValKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111207259	111152621	0	0
T1	7265	7173	0	0
T2	402081	401888	0	0
T3	403381	403238	0	0
T4	404332	404179	0	0
T5	401570	401308	0	0
T6	406098	405861	0	0
T7	401957	401736	0	0
T18	401209	401092	0	0
T19	7538	7487	0	0
T20	12815	12720	0	0

USBRxEnableKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111207259	111152621	0	0
T1	7265	7173	0	0
T2	402081	401888	0	0
T3	403381	403238	0	0
T4	404332	404179	0	0
T5	401570	401308	0	0
T6	406098	405861	0	0
T7	401957	401736	0	0
T18	401209	401092	0	0
T19	7538	7487	0	0
T20	12815	12720	0	0

USBTxDKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111207259	111152621	0	0
T1	7265	7173	0	0
T2	402081	401888	0	0
T3	403381	403238	0	0
T4	404332	404179	0	0
T5	401570	401308	0	0
T6	406098	405861	0	0
T7	401957	401736	0	0
T18	401209	401092	0	0
T19	7538	7487	0	0
T20	12815	12720	0	0

USBTxSe0Known_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111207259	111152621	0	0
T1	7265	7173	0	0
T2	402081	401888	0	0
T3	403381	403238	0	0
T4	404332	404179	0	0
T5	401570	401308	0	0
T6	406098	405861	0	0
T7	401957	401736	0	0
T18	401209	401092	0	0
T19	7538	7487	0	0
T20	12815	12720	0	0