Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.08	96.75	67.23	93.93		87.50	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	218030532	12271	0	0
ep_in_enable_rd_A	218030532	851	0	0
ep_out_enable_rd_A	218030532	824	0	0
in_iso_rd_A	218030532	952	0	0
intr_enable_rd_A	218030532	1336	0	0
out_iso_rd_A	218030532	890	0	0
phy_config_rd_A	218030532	696	0	0
phy_pins_drive_rd_A	218030532	604	0	0
rxenable_setup_rd_A	218030532	687	0	0
set_nak_out_rd_A	218030532	1066	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218030532	12271	0	0
T49	3214	15	0	0
T50	6334	491	0	0
T51	4144	25	0	0
T80	6541	22	0	0
T82	2172	10	0	0
T83	13137	4	0	0
T161	11299	642	0	0
T162	2196	11	0	0
T163	6191	464	0	0
T164	6843	2	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218030532	851	0	0
T58	8091	54	0	0
T59	6702	3	0	0
T80	6541	17	0	0
T165	7178	118	0	0
T166	9338	6	0	0
T170	2964	11	0	0
T171	3516	4	0	0
T176	2113	19	0	0
T181	7438	71	0	0
T213	3669	2	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218030532	824	0	0
T56	2811	7	0	0
T58	8091	105	0	0
T59	6702	23	0	0
T80	6541	25	0	0
T165	7178	102	0	0
T170	2964	34	0	0
T171	3516	10	0	0
T176	2113	4	0	0
T181	7438	46	0	0
T213	3669	17	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218030532	952	0	0
T58	8091	85	0	0
T59	6702	19	0	0
T80	6541	47	0	0
T161	11299	5	0	0
T165	7178	57	0	0
T170	2964	36	0	0
T171	3516	11	0	0
T176	2113	26	0	0
T181	7438	13	0	0
T213	3669	32	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218030532	1336	0	0
T58	8091	52	0	0
T59	6702	54	0	0
T63	1412	7	0	0
T67	1280	11	0	0
T80	6541	4	0	0
T165	7178	81	0	0
T170	2964	12	0	0
T181	7438	43	0	0
T216	1406	26	0	0
T217	1406	7	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218030532	890	0	0
T56	2811	7	0	0
T58	8091	97	0	0
T59	6702	45	0	0
T80	6541	52	0	0
T165	7178	55	0	0
T170	2964	49	0	0
T171	3516	13	0	0
T176	2113	29	0	0
T181	7438	20	0	0
T213	3669	23	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218030532	696	0	0
T56	2811	3	0	0
T58	8091	81	0	0
T59	6702	14	0	0
T80	6541	30	0	0
T165	7178	48	0	0
T170	2964	5	0	0
T171	3516	12	0	0
T176	2113	17	0	0
T181	7438	53	0	0
T213	3669	2	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218030532	604	0	0
T56	2811	5	0	0
T58	8091	79	0	0
T59	6702	23	0	0
T80	6541	21	0	0
T161	11299	4	0	0
T165	7178	47	0	0
T170	2964	22	0	0
T171	3516	4	0	0
T176	2113	1	0	0
T181	7438	40	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218030532	687	0	0
T58	8091	46	0	0
T59	6702	15	0	0
T80	6541	52	0	0
T161	11299	5	0	0
T165	7178	43	0	0
T170	2964	32	0	0
T171	3516	10	0	0
T176	2113	31	0	0
T181	7438	33	0	0
T213	3669	1	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218030532	1066	0	0
T56	2811	7	0	0
T58	8091	44	0	0
T59	6702	40	0	0
T80	6541	59	0	0
T165	7178	60	0	0
T170	2964	49	0	0
T171	3516	20	0	0
T176	2113	8	0	0
T181	7438	67	0	0
T213	3669	7	0	0