Unified Coverage Report :: Module :: usbdev

Module : usbdev

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.08	96.75	67.23	93.93		87.50	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	89.08	96.75	67.23	93.93		87.50	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.08	96.75	67.23	93.93		87.50	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.49	96.34	88.53	97.17	45.31	94.22	97.36

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_event	100.00	100.00				100.00
gen_no_stubbed_memory.u_memory_1p	98.96	95.83	100.00			100.00	100.00
gen_no_stubbed_memory.u_tlul2sram	83.77	85.71	70.94			78.41	100.00
i_usbdev_iomux	82.50	100.00	80.00			100.00	50.00
intr_av_out_empty	81.39	90.00	55.56			80.00	100.00
intr_av_overflow	81.25	100.00	25.00			100.00	100.00
intr_av_setup_empty	81.39	90.00	55.56			80.00	100.00
intr_disconnected	89.58	100.00	58.33			100.00	100.00
intr_frame	81.25	100.00	25.00			100.00	100.00
intr_host_lost	81.25	100.00	25.00			100.00	100.00
intr_hw_pkt_received	86.94	90.00	77.78			80.00	100.00
intr_hw_pkt_sent	86.94	90.00	77.78			80.00	100.00
intr_link_in_err	81.25	100.00	25.00			100.00	100.00
intr_link_out_err	89.58	100.00	58.33			100.00	100.00
intr_link_reset	89.58	100.00	58.33			100.00	100.00
intr_link_resume	81.25	100.00	25.00			100.00	100.00
intr_link_suspend	81.25	100.00	25.00			100.00	100.00
intr_powered	89.58	100.00	58.33			100.00	100.00
intr_rx_bitstuff_err	81.25	100.00	25.00			100.00	100.00
intr_rx_crc_err	81.25	100.00	25.00			100.00	100.00
intr_rx_full	73.06	90.00	22.22			80.00	100.00
intr_rx_pid_err	81.25	100.00	25.00			100.00	100.00
tlul_assert_device	95.24	100.00				85.71	100.00
u_reg	95.91	98.24	96.42	100.00		97.79	87.10
usbdev_avoutfifo	89.34	97.62	70.83			88.89	100.00
usbdev_avsetupfifo	89.34	97.62	70.83			88.89	100.00
usbdev_csr_assert	100.00						100.00
usbdev_impl	80.66	91.45	82.38		45.31	84.18	100.00
usbdev_rxfifo	80.50	90.48	61.54			70.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : usbdev

	Line No.	Total	Covered	Percent
TOTAL		154	149	96.75
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
ALWAYS	211	5	5	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	252	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	255	1	1	100.00
CONT_ASSIGN	257	1	1	100.00
CONT_ASSIGN	305	1	1	100.00
CONT_ASSIGN	310	1	1	100.00
CONT_ASSIGN	313	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	341	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	343	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	345	1	1	100.00
CONT_ASSIGN	349	1	0	0.00
ALWAYS	372	0	0
ALWAYS	372	3	3	100.00
ALWAYS	380	0	0
ALWAYS	380	4	4	100.00
ALWAYS	389	0	0
ALWAYS	389	3	3	100.00
ALWAYS	396	0	0
ALWAYS	396	3	3	100.00
ALWAYS	403	0	0
ALWAYS	403	3	3	100.00
ALWAYS	410	0	0
ALWAYS	410	2	2	100.00
ALWAYS	423	5	5	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	436	1	0	0.00
CONT_ASSIGN	437	1	1	100.00
CONT_ASSIGN	438	1	1	100.00
CONT_ASSIGN	440	1	1	100.00
CONT_ASSIGN	445	1	0	0.00
CONT_ASSIGN	446	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
ALWAYS	453	3	3	100.00
ALWAYS	460	0	0
ALWAYS	460	3	3	100.00
ALWAYS	469	3	3	100.00
ALWAYS	481	3	3	100.00
ALWAYS	488	0	0
ALWAYS	488	3	3	100.00
ALWAYS	495	10	10	100.00
ALWAYS	514	3	3	100.00
ALWAYS	521	0	0
ALWAYS	521	3	3	100.00
ALWAYS	529	0	0
ALWAYS	529	3	3	100.00
ALWAYS	538	0	0
ALWAYS	538	3	3	100.00
CONT_ASSIGN	548	1	1	100.00
CONT_ASSIGN	549	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	663	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	666	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
CONT_ASSIGN	685	1	1	100.00
CONT_ASSIGN	688	1	1	100.00
ALWAYS	694	0	0
ALWAYS	694	8	8	100.00
CONT_ASSIGN	774	1	1	100.00
CONT_ASSIGN	775	1	1	100.00
CONT_ASSIGN	776	1	1	100.00
CONT_ASSIGN	777	1	1	100.00
CONT_ASSIGN	785	1	1	100.00
ALWAYS	794	8	8	100.00
CONT_ASSIGN	808	1	1	100.00
CONT_ASSIGN	809	0	0
CONT_ASSIGN	812	1	1	100.00
CONT_ASSIGN	813	1	1	100.00
CONT_ASSIGN	870	1	1	100.00
CONT_ASSIGN	871	1	1	100.00
CONT_ASSIGN	875	1	1	100.00
CONT_ASSIGN	1138	1	1	100.00
CONT_ASSIGN	1139	1	1	100.00
CONT_ASSIGN	1140	1	1	100.00
CONT_ASSIGN	1141	1	1	100.00
CONT_ASSIGN	1181	1	1	100.00
CONT_ASSIGN	1184	1	1	100.00
CONT_ASSIGN	1193	1	1	100.00
ALWAYS	1196	5	3	60.00
ALWAYS	1205	3	3	100.00
CONT_ASSIGN	1218	1	1	100.00
CONT_ASSIGN	1221	1	1	100.00
CONT_ASSIGN	1228	1	1	100.00
ALWAYS	1232	3	3	100.00
CONT_ASSIGN	1239	1	1	100.00
CONT_ASSIGN	1244	1	1	100.00
CONT_ASSIGN	1246	1	1	100.00
CONT_ASSIGN	1254	0	0
CONT_ASSIGN	1256	0	0
CONT_ASSIGN	1258	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
122	1	1
209	1	1
211	1	1
212	1	1
214	1	1
215	1	1
217	1	1
246	1	1
247	1	1
248	1	1
252	1	1
253	1	1
255	1	1
257	1	1
305	1	1
310	1	1
313	1	1
316	1	1
341	1	1
342	1	1
343	1	1
344	1	1
345	1	1
349	0	1
372	1	1
373	1	1
374	1	1
380	1	1
381	1	1
382	1	1
383	1	1
389	1	1
390	1	1
391	1	1
396	1	1
397	1	1
398	1	1
403	1	1
404	1	1
405	1	1
410	1	1
411	1	1
423	1	1
424	1	1
425	1	1
427	1	1
428	1	1
431	1	1
432	1	1
436	0	1
437	1	1
438	1	1
440	1	1
445	0	1
446	1	1
447	1	1
449	1	1
453	1	1
454	1	1
455	1	1
			MISSING_ELSE
460	1	1
461	1	1
462	1	1
469	1	1
470	1	1
471	1	1
481	1	1
482	1	1
483	1	1
			MISSING_ELSE
488	1	1
489	1	1
490	1	1
495	1	1
496	1	1
497	1	1
498	1	1
499	1	1
501	1	1
503	1	1
504	1	1
505	1	1
507	1	1
			MISSING_ELSE
514	1	1
515	2	2
			MISSING_ELSE
521	1	1
522	1	1
523	1	1
529	1	1
530	1	1
531	1	1
538	1	1
539	1	1
540	1	1
548	1	1
549	1	1
550	1	1
663	1	1
664	1	1
666	1	1
667	1	1
685	1	1
688	1	1
694	1	1
695	1	1
696	1	1
697	1	1
698	1	1
699	1	1
701	1	1
702	1	1
774	1	1
775	1	1
776	1	1
777	1	1
785	1	1
794	1	1
795	1	1
796	1	1
797	1	1
799	1	1
800	1	1
802	1	1
803	1	1
			MISSING_ELSE
808	1	1
809		unreachable
812	1	1
813	1	1
870	1	1
871	1	1
875	1	1
1138	1	1
1139	1	1
1140	1	1
1141	1	1
1181	1	1
1184	1	1
1193	1	1
1196	1	1
1197	1	1
1198	0	1
1199	1	1
1200	0	1
			MISSING_ELSE
1205	1	1
1206	1	1
1208	1	1
1218	1	1
1221	1	1
1228	1	1
1232	1	1
1233	1	1
1235	1	1
1239	1	1
1244	1	1
1246	1	1
1254		unreachable
1256		unreachable
1258		unreachable

---

Cond Coverage for Module : usbdev

	Total	Covered	Percent
Conditions	119	80	67.23
Logical	119	80	67.23
Non-Logical	0	0
Event	0	0

 LINE       209
 EXPRESSION (ns_cnt == 6'd47)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       246
 EXPRESSION (reg2hw.fifo_ctrl.avsetup_rst.qe & reg2hw.fifo_ctrl.avsetup_rst.q)
             ---------------1---------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T46,T33,T48
1	0	Covered	T46,T33,T48
1	1	Covered	T46,T33,T48

 LINE       247
 EXPRESSION (reg2hw.fifo_ctrl.avout_rst.qe & reg2hw.fifo_ctrl.avout_rst.q)
             --------------1--------------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T46,T33,T48
1	0	Covered	T46,T33,T48
1	1	Covered	T46,T33,T48

 LINE       248
 EXPRESSION (reg2hw.fifo_ctrl.rx_rst.qe & reg2hw.fifo_ctrl.rx_rst.q)
             -------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T46,T33,T48
1	1	Not Covered

 LINE       252
 EXPRESSION (connect_en & ((~avsetup_rvalid)))
             -----1----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T46,T33,T48
1	1	Covered	T1,T2,T3

 LINE       253
 EXPRESSION (connect_en & ((~avout_rvalid)))
             -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       255
 EXPRESSION ((reg2hw.avsetupbuffer.qe & ((~avsetup_fifo_wready))) | (reg2hw.avoutbuffer.qe & ((~avout_fifo_wready))))
             --------------------------1-------------------------   ------------------------2-----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       255
 SUB-EXPRESSION (reg2hw.avsetupbuffer.qe & ((~avsetup_fifo_wready)))
                 -----------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T46,T33,T48
1	1	Not Covered

 LINE       255
 SUB-EXPRESSION (reg2hw.avoutbuffer.qe & ((~avout_fifo_wready)))
                 ----------1----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       257
 EXPRESSION (connect_en & ((~rx_fifo_rvalid)))
             -----1----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       305
 EXPRESSION (reg2hw.rxfifo.ep.re | reg2hw.rxfifo.setup.re | reg2hw.rxfifo.size.re | reg2hw.rxfifo.buffer.re)
             ---------1---------   -----------2----------   ----------3----------   -----------4-----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Not Covered
1	0	0	0	Not Covered

 LINE       316
 EXPRESSION (rx_wready & (rx_depth < 4'((RXFifoDepth - 1))))
             ----1----   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       431
 EXPRESSION (in_xact_starting ? in_buf[in_xact_start_ep] : in_buf_q)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T9,T21

 LINE       432
 EXPRESSION (in_xact_starting ? in_size[in_xact_start_ep] : in_size_q)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T9,T21

 LINE       436
 EXPRESSION (reg2hw.out_data_toggle.status.qe & reg2hw.out_data_toggle.mask.qe)
             ----------------1---------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       445
 EXPRESSION (reg2hw.in_data_toggle.status.qe & reg2hw.in_data_toggle.mask.qe)
             ---------------1---------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       454
 EXPRESSION (in_ep_xact_end && in_endpoint_val)
             -------1------    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T9,T21

 LINE       482
 EXPRESSION (rx_wvalid && out_endpoint_val)
             ----1----    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       501
 EXPRESSION (setup_received & out_endpoint_val)
             -------1------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T11,T14,T15

 LINE       505
 EXPRESSION (in_ep_xact_end & in_endpoint_val)
             -------1------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T9,T21

 LINE       531
 EXPRESSION (reg2hw.configin[i].rdy.q | reg2hw.configin[i].pend.q)
             ------------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T9,T21

 LINE       539
 EXPRESSION (set_sending[i] | set_sentbit[i] | update_pend[i])
             -------1------   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T2,T9,T21
1	0	0	Covered	T2,T9,T21

 LINE       540
 EXPRESSION (((~set_sentbit[i])) & ((~update_pend[i])))
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       549
 EXPRESSION (cfg_pinflip ? 1'b0 : usb_pullup_en)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       550
 EXPRESSION (((!cfg_pinflip)) ? 1'b0 : usb_pullup_en)
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       667
 EXPRESSION (reg2hw.usbctrl.resume_link_active.qe & reg2hw.usbctrl.resume_link_active.q)
             ------------------1-----------------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       774
 EXPRESSION (usb_mem_b_req | sw_mem_a_req)
             ------1------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T14
1	0	Covered	T1,T2,T3

 LINE       775
 EXPRESSION (usb_mem_b_req ? usb_mem_b_write : sw_mem_a_write)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       776
 EXPRESSION (usb_mem_b_req ? usb_mem_b_addr : sw_mem_a_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       777
 EXPRESSION (usb_mem_b_req ? usb_mem_b_wdata : sw_mem_a_wdata)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       800
 EXPRESSION (usb_mem_b_req & ((!usb_mem_b_write)))
             ------1------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T9,T21

 LINE       808
 EXPRESSION (gen_no_stubbed_memory.mem_rvalid & ((!gen_no_stubbed_memory.mem_rsteering)))
             ----------------1---------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T9,T21
1	1	Covered	T10,T11,T14

 LINE       813
 EXPRESSION (gen_no_stubbed_memory.mem_b_read_q ? gen_no_stubbed_memory.mem_rdata : gen_no_stubbed_memory.mem_b_rdata_q)
             -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T9,T21

 LINE       875
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       1184
 EXPRESSION (use_diff_rcvr & ((~link_suspend)))
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       1193
 EXPRESSION (usb_rcvr_ok_counter_q == '0)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1197
 EXPRESSION (use_diff_rcvr & ((!usb_rx_enable_o)))
             ------1------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       1199
 EXPRESSION (us_tick && (usb_rcvr_ok_counter_q > '0))
             ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       1221
 EXPRESSION (usb_ref_disable ? 1'b0 : event_sof)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       1228
 EXPRESSION (usb_ref_pulse_o ? 1'b1 : ((((!link_active)) || host_lost || usb_ref_disable) ? 1'b0 : usb_ref_val_q))
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       1228
 SUB-EXPRESSION ((((!link_active)) || host_lost || usb_ref_disable) ? 1'b0 : usb_ref_val_q)
                 -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1228
 SUB-EXPRESSION (((!link_active)) || host_lost || usb_ref_disable)
                 --------1-------    ----2----    -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Covered	T1,T2,T3

 LINE       1244
 EXPRESSION (reg2hw.wake_control.suspend_req.qe & reg2hw.wake_control.suspend_req.q)
             -----------------1----------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       1246
 EXPRESSION (reg2hw.wake_control.wake_ack.qe & reg2hw.wake_control.wake_ack.q)
             ---------------1---------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Toggle Coverage for Module : usbdev

	Total	Covered	Percent
Totals	68	61	89.71
Total Bits	428	402	93.93
Total Bits 0->1	214	201	93.93
Total Bits 1->0	214	201	93.93

Ports	68	61	89.71
Port Bits	428	402	93.93
Port Bits 0->1	214	201	93.93
Port Bits 1->0	214	201	93.93

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
clk_aon_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_aon_ni	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T10,T47	Yes	T3,T10,T47	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T3,T6	Yes	T1,T3,T6	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T49,T50,T51	Yes	T49,T50,T51	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T4,T5	Yes	T1,T6,T4	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	OUTPUT
cio_usb_dp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_usb_dn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
usb_rx_d_i	No	No		No		INPUT
cio_usb_dp_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cio_usb_dp_en_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cio_usb_dn_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cio_usb_dn_en_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
usb_tx_se0_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
usb_tx_d_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cio_sense_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
usb_dp_pullup_o	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	OUTPUT
usb_dn_pullup_o	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	OUTPUT
usb_rx_enable_o	Yes	Yes	T49,T58,T59	Yes	T49,T58,T59	OUTPUT
usb_tx_use_d_se0_o	Yes	Yes	T49,T58,T51	Yes	T49,T58,T59	OUTPUT
usb_aon_suspend_req_o	Yes	Yes	T55,T60,T57	Yes	T55,T60,T57	OUTPUT
usb_aon_wake_ack_o	Yes	Yes	T49,T58,T59	Yes	T49,T58,T59	OUTPUT
usb_aon_bus_reset_i	Unreachable	Unreachable		Unreachable		INPUT
usb_aon_sense_lost_i	Unreachable	Unreachable		Unreachable		INPUT
usb_aon_wake_detect_active_i	Unreachable	Unreachable		Unreachable		INPUT
usb_ref_val_o	No	No		No		OUTPUT
usb_ref_pulse_o	No	No		No		OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
intr_pkt_received_o	Yes	Yes	T11,T14,T15	Yes	T11,T14,T15	OUTPUT
intr_pkt_sent_o	Yes	Yes	T2,T9,T21	Yes	T2,T9,T21	OUTPUT
intr_powered_o	Yes	Yes	T49,T61,T62	Yes	T49,T61,T62	OUTPUT
intr_disconnected_o	Yes	Yes	T49,T61,T63	Yes	T49,T61,T63	OUTPUT
intr_host_lost_o	Yes	Yes	T61,T62,T64	Yes	T61,T62,T64	OUTPUT
intr_link_reset_o	Yes	Yes	T61,T63,T62	Yes	T61,T63,T62	OUTPUT
intr_link_suspend_o	Yes	Yes	T61,T63,T64	Yes	T61,T63,T64	OUTPUT
intr_link_resume_o	Yes	Yes	T61,T62,T64	Yes	T61,T62,T64	OUTPUT
intr_av_out_empty_o	Yes	Yes	T61,T63,T64	Yes	T61,T63,T64	OUTPUT
intr_rx_full_o	Yes	Yes	T61,T63,T62	Yes	T61,T63,T62	OUTPUT
intr_av_overflow_o	Yes	Yes	T61,T62,T64	Yes	T61,T62,T64	OUTPUT
intr_link_in_err_o	Yes	Yes	T61,T63,T62	Yes	T61,T63,T62	OUTPUT
intr_link_out_err_o	Yes	Yes	T64,T65,T66	Yes	T64,T65,T66	OUTPUT
intr_rx_crc_err_o	Yes	Yes	T63,T62,T64	Yes	T63,T62,T64	OUTPUT
intr_rx_pid_err_o	Yes	Yes	T61,T64,T67	Yes	T61,T64,T67	OUTPUT
intr_rx_bitstuff_err_o	Yes	Yes	T61,T63,T64	Yes	T61,T63,T64	OUTPUT
intr_frame_o	Yes	Yes	T61,T63,T64	Yes	T61,T63,T64	OUTPUT
intr_av_setup_empty_o	Yes	Yes	T61,T62,T64	Yes	T61,T62,T64	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : usbdev

	Line No.	Total	Covered	Percent
Branches		48	42	87.50
TERNARY	431	2	2	100.00
TERNARY	432	2	2	100.00
TERNARY	549	2	1	50.00
TERNARY	550	2	1	50.00
TERNARY	1221	2	1	50.00
TERNARY	1228	3	2	66.67
TERNARY	775	2	2	100.00
TERNARY	776	2	2	100.00
TERNARY	777	2	2	100.00
TERNARY	813	2	2	100.00
IF	211	3	3	100.00
IF	423	2	2	100.00
IF	454	2	2	100.00
IF	482	2	2	100.00
IF	497	4	4	100.00
IF	515	2	2	100.00
IF	697	2	2	100.00
IF	1197	3	1	33.33
IF	1205	2	2	100.00
IF	1232	2	2	100.00
IF	794	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	431	(in_xact_starting) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	432	(in_xact_starting) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	549	(cfg_pinflip) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	550	((!cfg_pinflip)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	1221	(usb_ref_disable) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1228	(usb_ref_pulse_o) ? 
-2-:	1228	((((!link_active) || host_lost) || usb_ref_disable)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	775	(usb_mem_b_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	776	(usb_mem_b_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	777	(usb_mem_b_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	813	(gen_no_stubbed_memory.mem_b_read_q) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	211	if ((!rst_n))
-2-:	214	if (us_tick)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	423	if ((!rst_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	454	if ((in_ep_xact_end && in_endpoint_val))

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	if ((rx_wvalid && out_endpoint_val))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	497	if (event_link_reset)
-2-:	501	if ((setup_received & out_endpoint_val))
-3-:	505	if ((in_ep_xact_end & in_endpoint_val))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T11,T14,T15
0	0	1	Covered	T2,T9,T21
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	515	if (in_xact_starting)

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	697	if (((setup_received && out_endpoint_val) && (out_endpoint == 4'((unsigned'(i))))))

Branches:

-1-	Status	Tests
1	Covered	T11,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1197	if ((use_diff_rcvr & (!usb_rx_enable_o)))
-2-:	1199	if ((us_tick && (usb_rcvr_ok_counter_q > '0)))

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1205	if ((!rst_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1232	if ((!rst_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	794	if ((!rst_ni))
-2-:	802	if (gen_no_stubbed_memory.mem_b_read_q)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T9,T21
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : usbdev

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	35	35	100.00	35	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	35	35	100.00	35	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertsKnown_A	217283345	217190680	0	0
CIODnEnKnown_A	217283345	217190680	0	0
CIODnKnown_A	217283345	217190680	0	0
CIODpEnKnown_A	217283345	217190680	0	0
CIODpKnown_A	217283345	217190680	0	0
FpvSecCmRegWeOnehotCheck_A	217283345	60	0	0
TlOAReadyKnown_A	217283345	217190680	0	0
TlODValidKnown_A	217283345	217190680	0	0
USBAonSuspendReqKnown_A	217283345	217190680	0	0
USBAonWakeAckKnown_A	217283345	217190680	0	0
USBDnPUKnown_A	217283345	217190680	0	0
USBDpPUKnown_A	217283345	217190680	0	0
USBIntrAvOutEmptyKnown_A	217283345	217190680	0	0
USBIntrAvOverKnown_A	217283345	217190680	0	0
USBIntrAvSetupEmptyKnown_A	217283345	217190680	0	0
USBIntrDisConKnown_A	217283345	217190680	0	0
USBIntrFrameKnown_A	217283345	217190680	0	0
USBIntrHostLostKnown_A	217283345	217190680	0	0
USBIntrLinkInErrKnown_A	217283345	217190680	0	0
USBIntrLinkOutErrKnown_A	217283345	217190680	0	0
USBIntrLinkResKnown_A	217283345	217190680	0	0
USBIntrLinkRstKnown_A	217283345	217190680	0	0
USBIntrLinkSusKnown_A	217283345	217190680	0	0
USBIntrPktRcvdKnown_A	217283345	217190680	0	0
USBIntrPktSentKnown_A	217283345	217190680	0	0
USBIntrPwrdKnown_A	217283345	217190680	0	0
USBIntrRxBitstuffErrKnown_A	217283345	217190680	0	0
USBIntrRxCrCErrKnown_A	217283345	217190680	0	0
USBIntrRxFullKnown_A	217283345	217190680	0	0
USBIntrRxPidErrKnown_A	217283345	217190680	0	0
USBRefPulseKnown_A	217283345	217190680	0	0
USBRefValKnown_A	217283345	217190680	0	0
USBRxEnableKnown_A	217283345	217190680	0	0
USBTxDKnown_A	217283345	217190680	0	0
USBTxSe0Known_A	217283345	217190680	0	0

AlertsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

CIODnEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

CIODnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

CIODpEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

CIODpKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	60	0	0
T25	1427	0	0	0
T36	406808	0	0	0
T52	5703	10	0	0
T53	0	20	0	0
T54	0	10	0	0
T68	0	10	0	0
T69	0	10	0	0
T70	11293	0	0	0
T71	401893	0	0	0
T72	7835	0	0	0
T73	402627	0	0	0
T74	401799	0	0	0
T75	14668	0	0	0
T76	401567	0	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

USBAonSuspendReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

USBAonWakeAckKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

USBDnPUKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

USBDpPUKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

USBIntrAvOutEmptyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

USBIntrAvOverKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

USBIntrAvSetupEmptyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

USBIntrDisConKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

USBIntrFrameKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

USBIntrHostLostKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

USBIntrLinkInErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

USBIntrLinkOutErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

USBIntrLinkResKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

USBIntrLinkRstKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

USBIntrLinkSusKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

USBIntrPktRcvdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

USBIntrPktSentKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

USBIntrPwrdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

USBIntrRxBitstuffErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

USBIntrRxCrCErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

USBIntrRxFullKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

USBIntrRxPidErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

USBRefPulseKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

USBRefValKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

USBRxEnableKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

USBTxDKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

USBTxSe0Known_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0