Unified Coverage Report :: Module Instance :: tb.dut.usbdev_avsetupfifo

Module Instance : tb.dut.usbdev_avsetupfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.58	100.00	70.83			87.50	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.34	97.62	70.83			88.89	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.08	96.75	67.23	93.93		87.50	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	92.50	95.00				90.00

Module Instance : tb.dut.usbdev_avoutfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.58	100.00	70.83			87.50	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.34	97.62	70.83			88.89	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.08	96.75	67.23	93.93		87.50	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	92.50	95.00				90.00

Module Instance : tb.dut.usbdev_rxfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.38	100.00	61.54			80.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.50	90.48	61.54			70.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.08	96.75	67.23	93.93		87.50	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	70.00	80.00				60.00

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	182	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
182	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Covered	Percent
Conditions	24	17	70.83
Logical	24	17	70.83
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (3'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T46,T33,T48

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T46,T33,T48

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T46,T33,T48
1	1	0	Not Covered
1	1	1	Covered	T11,T14,T15

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T46,T33,T48
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T46,T33,T48

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T46,T33,T48

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
Branches		8	7	87.50
TERNARY	88	3	2	66.67
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T46,T33,T48
0	1	Covered	T1,T2,T3
0	0	Not Covered

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T46,T33,T48
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	217283345	20239785	0	0
DepthKnown_A	217283345	217190680	0	0
RvalidKnown_A	217283345	217190680	0	0
WreadyKnown_A	217283345	217190680	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	217283345	20239785	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	20239785	0	0
T11	406794	400043	0	0
T14	0	400009	0	0
T15	0	399929	0	0
T17	403542	0	0	0
T22	405113	0	0	0
T33	6389	4213	0	0
T34	10495	7776	0	0
T43	0	400011	0	0
T46	2688	2139	0	0
T47	401770	0	0	0
T48	7878	6709	0	0
T77	3319	2503	0	0
T78	0	2365	0	0
T79	401351	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	20239785	0	0
T11	406794	400043	0	0
T14	0	400009	0	0
T15	0	399929	0	0
T17	403542	0	0	0
T22	405113	0	0	0
T33	6389	4213	0	0
T34	10495	7776	0	0
T43	0	400011	0	0
T46	2688	2139	0	0
T47	401770	0	0	0
T48	7878	6709	0	0
T77	3319	2503	0	0
T78	0	2365	0	0
T79	401351	0	0	0

Line Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	182	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
182	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Covered	Percent
Conditions	24	17	70.83
Logical	24	17	70.83
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (4'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T46,T33,T48

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T46,T33,T48
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T46,T33,T48

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
Branches		8	7	87.50
TERNARY	88	3	2	66.67
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T46,T33,T48
0	1	Covered	T1,T2,T3
0	0	Not Covered

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	217283345	176324197	0	0
DepthKnown_A	217283345	217190680	0	0
RvalidKnown_A	217283345	217190680	0	0
WreadyKnown_A	217283345	217190680	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	217283345	176324197	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	176324197	0	0
T1	402783	401519	0	0
T2	406117	402236	0	0
T3	401730	400791	0	0
T4	401258	0	0	0
T5	402543	401981	0	0
T6	401695	400299	0	0
T7	404716	404177	0	0
T8	402382	401814	0	0
T9	404217	401105	0	0
T10	401667	399921	0	0
T21	0	401822	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	176324197	0	0
T1	402783	401519	0	0
T2	406117	402236	0	0
T3	401730	400791	0	0
T4	401258	0	0	0
T5	402543	401981	0	0
T6	401695	400299	0	0
T7	404716	404177	0	0
T8	402382	401814	0	0
T9	404217	401105	0	0
T10	401667	399921	0	0
T21	0	401822	0	0

Line Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Covered	Percent
Conditions	26	16	61.54
Logical	26	16	61.54
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (4'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
Branches		10	8	80.00
TERNARY	88	3	1	33.33
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Not Covered

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	217283345	46201	0	0
DepthKnown_A	217283345	217190680	0	0
RvalidKnown_A	217283345	217190680	0	0
WreadyKnown_A	217283345	217190680	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	217283345	46201	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	46201	0	0
T1	402783	107	0	0
T2	406117	99	0	0
T3	401730	107	0	0
T4	401258	0	0	0
T5	402543	0	0	0
T6	401695	100	0	0
T7	404716	123	0	0
T8	402382	0	0	0
T9	404217	104	0	0
T10	401667	99	0	0
T13	0	144	0	0
T21	0	99	0	0
T45	0	101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	217190680	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	217283345	46201	0	0
T1	402783	107	0	0
T2	406117	99	0	0
T3	401730	107	0	0
T4	401258	0	0	0
T5	402543	0	0	0
T6	401695	100	0	0
T7	404716	123	0	0
T8	402382	0	0	0
T9	404217	104	0	0
T10	401667	99	0	0
T13	0	144	0	0
T21	0	99	0	0
T45	0	101	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	218030532	245288	0	0
DepthKnown_A	218030532	217915610	0	0
RvalidKnown_A	218030532	217915610	0	0
WreadyKnown_A	218030532	217915610	0	0
gen_passthru_fifo.paramCheckPass	800	800	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218030532	245288	0	0
T1	402783	8	0	0
T2	406117	17	0	0
T3	401730	8	0	0
T4	401258	9	0	0
T5	402543	12	0	0
T6	401695	8	0	0
T7	404716	16	0	0
T8	402382	12	0	0
T9	404217	17	0	0
T10	401667	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218030532	217915610	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218030532	217915610	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218030532	217915610	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	800	800	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	218030532	300087	0	0
DepthKnown_A	218030532	217915610	0	0
RvalidKnown_A	218030532	217915610	0	0
WreadyKnown_A	218030532	217915610	0	0
gen_passthru_fifo.paramCheckPass	800	800	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218030532	300087	0	0
T1	402783	41	0	0
T2	406117	17	0	0
T3	401730	8	0	0
T4	401258	9	0	0
T5	402543	12	0	0
T6	401695	39	0	0
T7	404716	16	0	0
T8	402382	12	0	0
T9	404217	77	0	0
T10	401667	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218030532	217915610	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218030532	217915610	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218030532	217915610	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	800	800	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	218030532	37132	0	0
DepthKnown_A	218030532	217915610	0	0
RvalidKnown_A	218030532	217915610	0	0
WreadyKnown_A	218030532	217915610	0	0
gen_passthru_fifo.paramCheckPass	800	800	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218030532	37132	0	0
T10	401667	2	0	0
T11	0	18	0	0
T13	402913	0	0	0
T14	0	18	0	0
T15	0	18	0	0
T17	403542	0	0	0
T18	401814	0	0	0
T19	402033	0	0	0
T21	405271	0	0	0
T33	6389	0	0	0
T35	0	2	0	0
T36	0	18	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	18	0	0
T44	0	2	0	0
T45	403601	0	0	0
T46	2688	0	0	0
T47	401770	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218030532	217915610	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218030532	217915610	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218030532	217915610	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	800	800	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	218030532	43732	0	0
DepthKnown_A	218030532	217915610	0	0
RvalidKnown_A	218030532	217915610	0	0
WreadyKnown_A	218030532	217915610	0	0
gen_passthru_fifo.paramCheckPass	800	800	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218030532	43732	0	0
T10	401667	2	0	0
T11	0	18	0	0
T13	402913	0	0	0
T14	0	18	0	0
T15	0	18	0	0
T17	403542	0	0	0
T18	401814	0	0	0
T19	402033	0	0	0
T21	405271	0	0	0
T33	6389	0	0	0
T35	0	2	0	0
T36	0	108	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	18	0	0
T44	0	2	0	0
T45	403601	0	0	0
T46	2688	0	0	0
T47	401770	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218030532	217915610	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218030532	217915610	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218030532	217915610	0	0
T1	402783	402695	0	0
T2	406117	405965	0	0
T3	401730	401667	0	0
T4	401258	401089	0	0
T5	402543	402411	0	0
T6	401695	401623	0	0
T7	404716	404568	0	0
T8	402382	402240	0	0
T9	404217	404071	0	0
T10	401667	401457	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	800	800	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0