Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	47143	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	53991	1		T1	27		T2	3		T3	3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	39275	1		T1	26		T2	4		T3	3
values[0x0]	30237	1		T1	7		T2	3		T3	3
values[0x1]	31622	1		T1	6		T2	5		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	37518	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	63616	1		T1	29		T2	9		T3	3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	488	1		T7	1		T10	1		T43	8
valid_sources[0x01]	398	1		T10	5		T43	5		T78	5
valid_sources[0x02]	425	1		T10	3		T43	2		T44	3
valid_sources[0x03]	364	1		T9	1		T10	5		T44	5
valid_sources[0x04]	307	1		T9	1		T10	6		T43	7
valid_sources[0x05]	378	1		T10	1		T43	5		T24	1
valid_sources[0x06]	446	1		T10	3		T43	3		T78	4
valid_sources[0x07]	386	1		T10	1		T43	7		T44	2
valid_sources[0x08]	489	1		T10	5		T43	7		T44	2
valid_sources[0x09]	384	1		T7	1		T10	4		T43	7
valid_sources[0x0a]	319	1		T10	3		T43	9		T19	2
valid_sources[0x0b]	381	1		T10	2		T43	10		T19	2
valid_sources[0x0c]	412	1		T10	7		T43	1		T44	4
valid_sources[0x0d]	333	1		T9	1		T10	3		T43	2
valid_sources[0x0e]	484	1		T10	4		T43	3		T27	2
valid_sources[0x0f]	546	1		T10	9		T43	4		T208	2
valid_sources[0x10]	341	1		T10	11		T43	6		T78	1
valid_sources[0x11]	511	1		T10	4		T43	4		T78	6
valid_sources[0x12]	458	1		T10	1		T43	2		T44	1
valid_sources[0x13]	309	1		T10	5		T43	4		T44	2
valid_sources[0x14]	334	1		T10	4		T43	4		T78	4
valid_sources[0x15]	331	1		T10	8		T43	2		T78	3
valid_sources[0x16]	358	1		T7	1		T10	6		T43	5
valid_sources[0x17]	412	1		T6	1		T9	1		T10	6
valid_sources[0x18]	308	1		T10	4		T43	4		T44	1
valid_sources[0x19]	409	1		T10	2		T43	4		T44	2
valid_sources[0x1a]	306	1		T2	12		T10	6		T43	7
valid_sources[0x1b]	298	1		T10	4		T43	5		T26	2
valid_sources[0x1c]	381	1		T10	5		T43	4		T27	1
valid_sources[0x1d]	431	1		T10	5		T43	8		T78	7
valid_sources[0x1e]	369	1		T10	6		T43	8		T44	2
valid_sources[0x1f]	330	1		T9	1		T10	6		T43	5
valid_sources[0x20]	771	1		T10	6		T43	2		T27	1
valid_sources[0x21]	442	1		T10	3		T43	8		T44	1
valid_sources[0x22]	371	1		T10	5		T43	2		T16	1
valid_sources[0x23]	350	1		T10	4		T43	4		T208	2
valid_sources[0x24]	330	1		T8	1		T10	4		T43	5
valid_sources[0x25]	338	1		T5	1		T7	1		T9	1
valid_sources[0x26]	327	1		T10	4		T43	4		T39	1
valid_sources[0x27]	316	1		T10	9		T43	1		T44	2
valid_sources[0x28]	438	1		T7	2		T10	14		T43	8
valid_sources[0x29]	319	1		T10	3		T43	5		T44	4
valid_sources[0x2a]	330	1		T10	2		T43	2		T247	8
valid_sources[0x2b]	406	1		T10	5		T43	1		T78	5
valid_sources[0x2c]	403	1		T10	5		T43	4		T39	1
valid_sources[0x2d]	418	1		T6	1		T10	8		T43	2
valid_sources[0x2e]	394	1		T10	4		T44	12		T78	5
valid_sources[0x2f]	313	1		T10	9		T43	3		T248	2
valid_sources[0x30]	372	1		T10	2		T43	6		T44	6
valid_sources[0x31]	489	1		T10	11		T43	5		T44	6
valid_sources[0x32]	422	1		T10	7		T43	13		T78	6
valid_sources[0x33]	340	1		T10	9		T43	3		T44	6
valid_sources[0x34]	293	1		T8	1		T10	5		T43	4
valid_sources[0x35]	460	1		T6	1		T10	7		T43	5
valid_sources[0x36]	409	1		T10	2		T43	3		T44	3
valid_sources[0x37]	464	1		T10	9		T43	8		T78	6
valid_sources[0x38]	383	1		T10	3		T43	3		T44	5
valid_sources[0x39]	345	1		T10	5		T43	10		T78	3
valid_sources[0x3a]	296	1		T10	3		T43	4		T26	1
valid_sources[0x3b]	260	1		T43	2		T78	1		T248	6
valid_sources[0x3c]	393	1		T10	6		T43	3		T44	1
valid_sources[0x3d]	322	1		T6	2		T10	3		T43	5
valid_sources[0x3e]	310	1		T10	5		T43	11		T78	1
valid_sources[0x3f]	413	1		T10	7		T43	5		T44	1
valid_sources[0x40]	319	1		T5	2		T10	3		T43	1
valid_sources[0x41]	393	1		T7	2		T10	3		T43	3
valid_sources[0x42]	369	1		T10	2		T43	3		T78	8
valid_sources[0x43]	393	1		T10	1		T43	2		T44	2
valid_sources[0x44]	279	1		T10	2		T43	9		T44	1
valid_sources[0x45]	390	1		T7	1		T10	6		T43	1
valid_sources[0x46]	368	1		T10	4		T43	3		T24	1
valid_sources[0x47]	388	1		T5	4		T10	6		T43	3
valid_sources[0x48]	372	1		T10	6		T43	3		T78	3
valid_sources[0x49]	353	1		T7	1		T10	8		T43	2
valid_sources[0x4a]	476	1		T10	1		T43	5		T44	1
valid_sources[0x4b]	366	1		T9	1		T10	4		T43	9
valid_sources[0x4c]	312	1		T10	4		T43	4		T44	6
valid_sources[0x4d]	310	1		T10	8		T43	7		T78	6
valid_sources[0x4e]	432	1		T10	3		T26	4		T44	5
valid_sources[0x4f]	372	1		T10	7		T43	6		T44	3
valid_sources[0x50]	326	1		T10	2		T43	5		T44	3
valid_sources[0x51]	1310	1		T10	3		T44	1		T78	4
valid_sources[0x52]	1407	1		T10	4		T43	6		T19	3
valid_sources[0x53]	296	1		T10	5		T43	2		T44	2
valid_sources[0x54]	337	1		T10	3		T43	9		T44	4
valid_sources[0x55]	365	1		T5	1		T10	4		T43	6
valid_sources[0x56]	350	1		T10	10		T43	3		T78	2
valid_sources[0x57]	286	1		T9	1		T10	2		T43	1
valid_sources[0x58]	303	1		T7	1		T10	2		T43	4
valid_sources[0x59]	358	1		T10	5		T43	5		T27	1
valid_sources[0x5a]	343	1		T10	6		T43	1		T44	3
valid_sources[0x5b]	427	1		T10	5		T43	8		T44	5
valid_sources[0x5c]	342	1		T10	5		T43	7		T44	5
valid_sources[0x5d]	309	1		T10	1		T43	4		T44	2
valid_sources[0x5e]	524	1		T10	6		T43	5		T19	1
valid_sources[0x5f]	336	1		T10	9		T43	8		T44	2
valid_sources[0x60]	364	1		T10	5		T43	1		T44	18
valid_sources[0x61]	398	1		T10	3		T43	6		T44	3
valid_sources[0x62]	353	1		T10	10		T43	8		T27	1
valid_sources[0x63]	337	1		T10	8		T43	6		T19	2
valid_sources[0x64]	384	1		T10	5		T43	2		T208	2
valid_sources[0x65]	368	1		T10	2		T43	3		T78	1
valid_sources[0x66]	286	1		T10	5		T43	10		T44	2
valid_sources[0x67]	461	1		T10	3		T43	4		T44	1
valid_sources[0x68]	370	1		T10	2		T43	1		T78	2
valid_sources[0x69]	317	1		T10	5		T43	5		T44	3
valid_sources[0x6a]	399	1		T10	2		T43	3		T19	3
valid_sources[0x6b]	308	1		T5	2		T10	5		T43	7
valid_sources[0x6c]	493	1		T43	3		T78	2		T25	1
valid_sources[0x6d]	363	1		T10	1		T43	2		T248	7
valid_sources[0x6e]	1684	1		T10	6		T43	2		T78	6
valid_sources[0x6f]	448	1		T10	8		T43	3		T39	1
valid_sources[0x70]	320	1		T10	7		T43	7		T78	8
valid_sources[0x71]	333	1		T10	13		T43	7		T78	4
valid_sources[0x72]	424	1		T10	2		T43	5		T44	1
valid_sources[0x73]	343	1		T10	7		T43	4		T44	4
valid_sources[0x74]	326	1		T10	5		T43	4		T17	1
valid_sources[0x75]	469	1		T10	5		T43	8		T39	1
valid_sources[0x76]	373	1		T10	1		T43	4		T26	6
valid_sources[0x77]	428	1		T10	7		T43	3		T27	1
valid_sources[0x78]	400	1		T10	8		T43	6		T24	1
valid_sources[0x79]	308	1		T7	1		T10	6		T43	6
valid_sources[0x7a]	348	1		T10	7		T43	9		T44	12
valid_sources[0x7b]	386	1		T6	1		T9	1		T10	4
valid_sources[0x7c]	317	1		T5	7		T10	5		T43	4
valid_sources[0x7d]	406	1		T9	1		T10	1		T43	6
valid_sources[0x7e]	431	1		T43	2		T44	2		T78	2
valid_sources[0x7f]	389	1		T10	1		T43	5		T78	5
valid_sources[0x80]	311	1		T10	5		T43	3		T44	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

21116

1

T1

21

T3

1

T4

1

values[0x0]

all_enables

biggest_size

18282

1

T1

4

T2

2

T3

2

values[0x1]

all_enables

biggest_size

14593

1

T1

2

T2

1

T4

3