Summary for Variable cp_num_num_enable_bytes
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_num_num_enable_bytes
Bins
| | | | | | | | | | | |
partial |
61049 |
1 |
|
T1 |
12 |
|
T2 |
9 |
|
T3 |
5 |
full_word |
55003 |
1 |
|
T1 |
27 |
|
T2 |
3 |
|
T3 |
3 |
Summary for Variable cp_tl_intg_err_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
4 |
3 |
1 |
25.00 |
Automatically Generated Bins for cp_tl_intg_err_type
Uncovered bins
| | | |
auto[TlIntgErrCmd] |
0 |
1 |
1 |
auto[TlIntgErrData] |
0 |
1 |
1 |
auto[TlIntgErrBoth] |
0 |
1 |
1 |
Covered bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
116052 |
1 |
|
T1 |
39 |
|
T2 |
12 |
|
T3 |
8 |
Summary for Variable cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_write
Bins
| | | | | | | | | | | |
auto[0] |
41089 |
1 |
|
T1 |
26 |
|
T2 |
4 |
|
T3 |
3 |
auto[1] |
74963 |
1 |
|
T1 |
13 |
|
T2 |
8 |
|
T3 |
5 |
Summary for Cross cr_all
Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
12 |
4 |
25.00 |
12 |
Automatically Generated Cross Bins for cr_all
Element holes
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | NUMBER |
[auto[TlIntgErrCmd] , auto[TlIntgErrData] , auto[TlIntgErrBoth]] |
* |
* |
-- |
-- |
12 |
Covered bins
| | | | | | | | | | | | | |
auto[TlIntgErrNone] |
partial |
auto[0] |
19757 |
1 |
|
T1 |
5 |
|
T2 |
4 |
|
T3 |
2 |
auto[TlIntgErrNone] |
partial |
auto[1] |
41292 |
1 |
|
T1 |
7 |
|
T2 |
5 |
|
T3 |
3 |
auto[TlIntgErrNone] |
full_word |
auto[0] |
21332 |
1 |
|
T1 |
21 |
|
T3 |
1 |
|
T4 |
1 |
auto[TlIntgErrNone] |
full_word |
auto[1] |
33671 |
1 |
|
T1 |
6 |
|
T2 |
3 |
|
T3 |
2 |