Module Definition
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Module Instance : tb.dut.u_reg.u_wake_events_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
54.76 85.71 33.33 100.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
56.41 92.31 33.33 100.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
57.45 82.35 30.77 66.67 50.00 u_wake_events_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wake_control_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_wake_control_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wake_control_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
66.67 33.33 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00

Line Coverage for Module : prim_pulse_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Module : prim_pulse_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT2,T3,T4
01CoveredT61,T69,T62
10CoveredT61,T69,T62
11CoveredT69,T70,T97

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT2,T3,T4
01CoveredT61,T69,T62
10CoveredT69,T70,T97
11CoveredT61,T69,T62

Branch Coverage for Module : prim_pulse_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T2,T3,T4


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T2,T3,T4


Assert Coverage for Module : prim_pulse_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 546845827 1873 0 0
SrcPulseCheck_M 1057577519 1909 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 546845827 1873 0 0
T61 13808 4 0 0
T62 8277 20 0 0
T63 6657 4 0 0
T69 4252 28 0 0
T70 6154 24 0 0
T97 3125 4 0 0
T98 3179 4 0 0
T99 5229 22 0 0
T100 4339 4 0 0
T101 2604 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1057577519 1909 0 0
T61 13808 4 0 0
T62 8277 20 0 0
T63 6657 4 0 0
T69 4252 28 0 0
T70 6154 24 0 0
T97 3125 4 0 0
T98 3179 4 0 0
T99 5229 22 0 0
T100 4339 4 0 0
T101 2604 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL7685.71
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN97100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 0 1


Cond Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions6233.33
Logical6233.33
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT2,T3,T4
01Unreachable
10Not Covered
11Unreachable

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT2,T3,T4
01Not Covered
10Not Covered
11Not Covered

Branch Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T2,T3,T4


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T2,T3,T4


Assert Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 0 0.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 0 0.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 12038045 0 0 0
SrcPulseCheck_M 522769737 0 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12038045 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 522769737 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT2,T3,T4
01CoveredT61,T69,T62
10CoveredT61,T69,T62
11CoveredT69,T70,T97

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT2,T3,T4
01CoveredT61,T69,T62
10CoveredT69,T70,T97
11CoveredT61,T69,T62

Branch Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T2,T3,T4


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T2,T3,T4


Assert Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 12038045 925 0 0
SrcPulseCheck_M 522769737 961 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12038045 925 0 0
T61 64 2 0 0
T62 293 10 0 0
T63 214 2 0 0
T69 169 14 0 0
T70 230 12 0 0
T97 70 2 0 0
T98 30 2 0 0
T99 112 11 0 0
T100 154 2 0 0
T101 61 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 522769737 961 0 0
T61 13744 2 0 0
T62 7984 10 0 0
T63 6443 2 0 0
T69 4083 14 0 0
T70 5924 12 0 0
T97 3055 2 0 0
T98 3149 2 0 0
T99 5117 11 0 0
T100 4185 2 0 0
T101 2543 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT2,T3,T4
01CoveredT61,T69,T62
10CoveredT61,T69,T62
11CoveredT69,T70,T97

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT2,T3,T4
01CoveredT61,T69,T62
10CoveredT69,T70,T97
11CoveredT61,T69,T62

Branch Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T2,T3,T4


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T2,T3,T4


Assert Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 522769737 948 0 0
SrcPulseCheck_M 12038045 948 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 522769737 948 0 0
T61 13744 2 0 0
T62 7984 10 0 0
T63 6443 2 0 0
T69 4083 14 0 0
T70 5924 12 0 0
T97 3055 2 0 0
T98 3149 2 0 0
T99 5117 11 0 0
T100 4185 2 0 0
T101 2543 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 12038045 948 0 0
T61 64 2 0 0
T62 293 10 0 0
T63 214 2 0 0
T69 169 14 0 0
T70 230 12 0 0
T97 70 2 0 0
T98 30 2 0 0
T99 112 11 0 0
T100 154 2 0 0
T101 61 1 0 0

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