Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.86	92.59	67.16	92.89		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	519983849	10631	0	0
ep_in_enable_rd_A	519983849	3747	0	0
ep_out_enable_rd_A	519983849	3259	0	0
in_iso_rd_A	519983849	3644	0	0
intr_enable_rd_A	519983849	4644	0	0
out_iso_rd_A	519983849	2716	0	0
phy_config_rd_A	519983849	2173	0	0
phy_pins_drive_rd_A	519983849	2546	0	0
rxenable_setup_rd_A	519983849	3180	0	0
set_nak_out_rd_A	519983849	3123	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519983849	10631	0	0
T58	16020	1048	0	0
T59	3375	10	0	0
T60	3506	16	0	0
T102	31653	4	0	0
T209	40932	1	0	0
T210	108777	7	0	0
T212	11988	931	0	0
T213	6404	25	0	0
T237	6520	15	0	0
T249	20923	2	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519983849	3747	0	0
T66	7640	48	0	0
T99	3424	20	0	0
T209	40932	352	0	0
T210	108777	294	0	0
T239	7086	25	0	0
T248	8066	51	0	0
T249	20923	234	0	0
T263	5980	12	0	0
T264	8778	11	0	0
T267	16921	296	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519983849	3259	0	0
T66	7640	72	0	0
T99	3424	34	0	0
T209	40932	266	0	0
T210	108777	158	0	0
T239	7086	3	0	0
T248	8066	91	0	0
T249	20923	206	0	0
T263	5980	25	0	0
T264	8778	29	0	0
T267	16921	253	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519983849	3644	0	0
T66	7640	27	0	0
T99	3424	41	0	0
T209	40932	292	0	0
T210	108777	265	0	0
T239	7086	29	0	0
T248	8066	17	0	0
T249	20923	369	0	0
T263	5980	12	0	0
T264	8778	29	0	0
T267	16921	256	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519983849	4644	0	0
T58	16020	5	0	0
T66	7640	27	0	0
T70	1890	2	0	0
T99	3424	35	0	0
T209	40932	252	0	0
T210	108777	347	0	0
T249	20923	420	0	0
T263	5980	7	0	0
T264	8778	26	0	0
T268	2520	28	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519983849	2716	0	0
T66	7640	30	0	0
T99	3424	32	0	0
T209	40932	160	0	0
T210	108777	247	0	0
T239	7086	42	0	0
T248	8066	76	0	0
T249	20923	164	0	0
T263	5980	14	0	0
T264	8778	17	0	0
T267	16921	213	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519983849	2173	0	0
T66	7640	20	0	0
T209	40932	79	0	0
T210	108777	172	0	0
T239	7086	31	0	0
T246	2677	3	0	0
T248	8066	50	0	0
T249	20923	179	0	0
T263	5980	18	0	0
T264	8778	42	0	0
T267	16921	180	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519983849	2546	0	0
T58	16020	1	0	0
T66	7640	20	0	0
T209	40932	158	0	0
T210	108777	150	0	0
T239	7086	25	0	0
T246	2677	9	0	0
T248	8066	52	0	0
T249	20923	266	0	0
T263	5980	19	0	0
T264	8778	26	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519983849	3180	0	0
T66	7640	43	0	0
T99	3424	22	0	0
T209	40932	119	0	0
T210	108777	387	0	0
T239	7086	2	0	0
T246	2677	5	0	0
T248	8066	43	0	0
T249	20923	199	0	0
T263	5980	22	0	0
T264	8778	44	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519983849	3123	0	0
T66	7640	97	0	0
T99	3424	23	0	0
T209	40932	227	0	0
T210	108777	259	0	0
T239	7086	48	0	0
T246	2677	1	0	0
T248	8066	12	0	0
T249	20923	230	0	0
T263	5980	34	0	0
T264	8778	29	0	0