Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	319831	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	532764	1		T1	6		T2	3		T3	30

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	572654	1		T1	7		T2	2		T3	24
values[0x0]	139704	1		T1	2		T2	1		T3	8
values[0x1]	140237	1		T1	3		T2	4		T3	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	244791	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	607804	1		T1	12		T2	5		T3	36

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2984	1		T10	21		T11	252		T48	1
valid_sources[0x01]	2200	1		T10	38		T11	2		T219	1
valid_sources[0x02]	2888	1		T10	29		T11	2		T53	19
valid_sources[0x03]	3120	1		T1	1		T17	11		T10	15
valid_sources[0x04]	2454	1		T10	27		T88	1		T26	12
valid_sources[0x05]	2323	1		T10	27		T296	1		T12	39
valid_sources[0x06]	2946	1		T10	33		T137	9		T96	3
valid_sources[0x07]	2320	1		T10	25		T11	1		T38	1
valid_sources[0x08]	2528	1		T10	22		T11	1		T88	1
valid_sources[0x09]	2496	1		T10	23		T297	1		T45	1
valid_sources[0x0a]	2407	1		T10	29		T48	1		T298	1
valid_sources[0x0b]	2884	1		T10	29		T11	3		T88	1
valid_sources[0x0c]	3100	1		T10	29		T35	1		T12	45
valid_sources[0x0d]	3481	1		T10	31		T12	67		T214	60
valid_sources[0x0e]	3128	1		T10	21		T11	3		T96	2
valid_sources[0x0f]	5885	1		T10	27		T11	3		T93	1
valid_sources[0x10]	2890	1		T10	24		T11	4		T12	49
valid_sources[0x11]	2432	1		T10	32		T11	4		T38	1
valid_sources[0x12]	2937	1		T10	33		T11	2		T49	1
valid_sources[0x13]	2777	1		T2	1		T13	1		T10	39
valid_sources[0x14]	2558	1		T10	28		T11	160		T48	1
valid_sources[0x15]	2834	1		T17	22		T10	29		T11	124
valid_sources[0x16]	2370	1		T10	28		T11	3		T92	2
valid_sources[0x17]	2674	1		T10	25		T92	2		T275	19
valid_sources[0x18]	2660	1		T10	32		T11	6		T93	1
valid_sources[0x19]	2430	1		T10	17		T11	2		T92	1
valid_sources[0x1a]	2489	1		T10	28		T11	54		T14	1
valid_sources[0x1b]	2773	1		T10	37		T92	2		T179	1
valid_sources[0x1c]	3161	1		T10	28		T11	2		T32	3
valid_sources[0x1d]	6100	1		T10	24		T11	2		T162	1
valid_sources[0x1e]	3405	1		T16	1		T10	22		T11	390
valid_sources[0x1f]	2188	1		T10	26		T11	5		T47	1
valid_sources[0x20]	2306	1		T10	37		T46	1		T36	10
valid_sources[0x21]	5347	1		T10	27		T11	3		T12	44
valid_sources[0x22]	3804	1		T10	22		T57	1		T31	2
valid_sources[0x23]	2850	1		T10	28		T11	1		T12	54
valid_sources[0x24]	2242	1		T3	2		T10	33		T11	3
valid_sources[0x25]	2887	1		T10	27		T11	2		T4	2
valid_sources[0x26]	2448	1		T10	23		T11	5		T30	1
valid_sources[0x27]	5465	1		T18	1		T10	19		T11	2
valid_sources[0x28]	2891	1		T10	24		T11	334		T38	1
valid_sources[0x29]	2370	1		T10	27		T19	8		T11	4
valid_sources[0x2a]	2385	1		T10	26		T219	1		T53	23
valid_sources[0x2b]	3140	1		T10	20		T11	4		T88	2
valid_sources[0x2c]	2121	1		T1	2		T10	29		T11	1
valid_sources[0x2d]	2384	1		T3	4		T10	27		T11	1
valid_sources[0x2e]	2631	1		T10	28		T11	5		T38	1
valid_sources[0x2f]	3037	1		T10	26		T11	1		T162	1
valid_sources[0x30]	2290	1		T10	28		T11	1		T34	3
valid_sources[0x31]	2565	1		T10	27		T30	1		T162	1
valid_sources[0x32]	2628	1		T10	34		T11	6		T299	1
valid_sources[0x33]	2622	1		T10	18		T11	2		T179	1
valid_sources[0x34]	2797	1		T10	29		T11	175		T87	3
valid_sources[0x35]	2429	1		T3	1		T10	30		T11	1
valid_sources[0x36]	2311	1		T10	26		T11	1		T29	10
valid_sources[0x37]	2379	1		T3	2		T10	21		T11	4
valid_sources[0x38]	2822	1		T16	1		T10	20		T11	2
valid_sources[0x39]	2081	1		T10	26		T87	1		T88	1
valid_sources[0x3a]	2987	1		T10	27		T11	1		T15	11
valid_sources[0x3b]	2616	1		T16	1		T10	28		T11	7
valid_sources[0x3c]	2312	1		T10	20		T11	3		T298	1
valid_sources[0x3d]	2247	1		T10	25		T138	5		T92	5
valid_sources[0x3e]	2760	1		T10	27		T11	95		T14	1
valid_sources[0x3f]	2208	1		T18	1		T10	20		T11	2
valid_sources[0x40]	2486	1		T10	34		T11	5		T300	1
valid_sources[0x41]	2382	1		T10	25		T11	8		T57	1
valid_sources[0x42]	2325	1		T10	27		T11	1		T96	2
valid_sources[0x43]	2824	1		T10	26		T11	2		T92	2
valid_sources[0x44]	2210	1		T10	27		T11	3		T35	1
valid_sources[0x45]	2743	1		T2	2		T10	41		T91	2
valid_sources[0x46]	2384	1		T13	1		T10	28		T93	1
valid_sources[0x47]	2550	1		T10	21		T11	1		T48	2
valid_sources[0x48]	2317	1		T1	1		T10	29		T53	3
valid_sources[0x49]	2463	1		T10	27		T11	98		T301	1
valid_sources[0x4a]	2862	1		T10	38		T11	2		T302	1
valid_sources[0x4b]	2249	1		T10	36		T11	1		T12	75
valid_sources[0x4c]	2787	1		T16	1		T10	18		T48	2
valid_sources[0x4d]	2251	1		T10	31		T11	4		T47	1
valid_sources[0x4e]	2898	1		T10	22		T162	2		T12	70
valid_sources[0x4f]	2702	1		T2	1		T10	25		T11	2
valid_sources[0x50]	2677	1		T10	20		T11	6		T174	1
valid_sources[0x51]	2398	1		T10	25		T11	5		T27	2
valid_sources[0x52]	2949	1		T10	28		T11	132		T50	2
valid_sources[0x53]	3108	1		T10	23		T11	90		T46	1
valid_sources[0x54]	2438	1		T10	18		T11	4		T162	1
valid_sources[0x55]	2769	1		T10	36		T179	1		T12	72
valid_sources[0x56]	3024	1		T10	21		T11	1		T93	1
valid_sources[0x57]	2438	1		T10	26		T11	85		T48	1
valid_sources[0x58]	2326	1		T10	21		T11	2		T303	2
valid_sources[0x59]	2151	1		T10	29		T304	1		T50	8
valid_sources[0x5a]	5600	1		T10	27		T11	2		T88	1
valid_sources[0x5b]	2090	1		T10	28		T11	4		T14	1
valid_sources[0x5c]	2816	1		T1	2		T10	34		T11	500
valid_sources[0x5d]	3384	1		T10	27		T11	2		T34	5
valid_sources[0x5e]	2872	1		T10	21		T91	1		T305	4
valid_sources[0x5f]	2272	1		T10	25		T11	2		T34	1
valid_sources[0x60]	3047	1		T10	23		T11	2		T14	1
valid_sources[0x61]	2498	1		T10	26		T178	1		T174	1
valid_sources[0x62]	2448	1		T10	13		T34	1		T298	1
valid_sources[0x63]	3811	1		T10	19		T11	23		T48	1
valid_sources[0x64]	2755	1		T10	26		T11	1		T49	1
valid_sources[0x65]	5252	1		T10	26		T11	2926		T139	1
valid_sources[0x66]	2755	1		T13	1		T10	26		T11	2
valid_sources[0x67]	3945	1		T10	25		T11	1		T4	1
valid_sources[0x68]	2261	1		T10	24		T11	4		T88	1
valid_sources[0x69]	2944	1		T3	2		T10	34		T11	5
valid_sources[0x6a]	2765	1		T10	33		T11	1		T88	1
valid_sources[0x6b]	3307	1		T10	30		T11	3		T48	1
valid_sources[0x6c]	3133	1		T10	30		T11	1		T302	1
valid_sources[0x6d]	3163	1		T10	22		T11	3		T48	1
valid_sources[0x6e]	2722	1		T2	1		T10	29		T11	2
valid_sources[0x6f]	2893	1		T10	27		T12	70		T214	57
valid_sources[0x70]	3961	1		T10	20		T11	1		T93	1
valid_sources[0x71]	2961	1		T10	22		T11	260		T12	48
valid_sources[0x72]	2762	1		T10	41		T11	3		T219	1
valid_sources[0x73]	3109	1		T10	31		T11	42		T38	1
valid_sources[0x74]	2107	1		T3	2		T17	3		T10	21
valid_sources[0x75]	2926	1		T10	26		T96	8		T304	2
valid_sources[0x76]	3044	1		T10	32		T11	1		T88	1
valid_sources[0x77]	3079	1		T10	23		T11	1		T4	1
valid_sources[0x78]	3460	1		T10	30		T11	1		T91	1
valid_sources[0x79]	3049	1		T10	16		T11	2		T91	1
valid_sources[0x7a]	3062	1		T10	23		T11	4		T35	1
valid_sources[0x7b]	2701	1		T18	1		T10	19		T11	2
valid_sources[0x7c]	2563	1		T1	1		T10	42		T49	2
valid_sources[0x7d]	5682	1		T10	36		T11	3		T30	1
valid_sources[0x7e]	2243	1		T10	28		T47	1		T96	2
valid_sources[0x7f]	3378	1		T10	30		T14	1		T49	1
valid_sources[0x80]	3984	1		T10	23		T11	1		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

304132

1

T1

4

T3

19

T13

1

values[0x0]

all_enables

biggest_size

118286

1

T1

2

T2

1

T3

5

values[0x1]

all_enables

biggest_size

110346

1

T2

2

T3

6

T13

1