Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	332595	1		T1	6		T2	4		T3	12
full_word	533677	1		T1	6		T2	3		T3	30

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	866012	1		T1	12		T2	7		T3	42
auto[TlIntgErrCmd]	101	1		T102	2		T209	5		T210	8
auto[TlIntgErrData]	69	1		T102	4		T209	4		T210	4
auto[TlIntgErrBoth]	90	1		T102	4		T209	1		T210	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	574331	1		T1	7		T2	2		T3	24
auto[1]	291941	1		T1	5		T2	5		T3	18

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	269915	1		T1	3		T2	2		T3	5
auto[TlIntgErrNone]	partial	auto[1]	62439	1		T1	3		T2	2		T3	7
auto[TlIntgErrNone]	full_word	auto[0]	304306	1		T1	4		T3	19		T13	1
auto[TlIntgErrNone]	full_word	auto[1]	229352	1		T1	2		T2	3		T3	11
auto[TlIntgErrCmd]	partial	auto[0]	38	1		T210	2		T249	1		T286	1
auto[TlIntgErrCmd]	partial	auto[1]	56	1		T102	2		T209	5		T210	5
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T210	1		T286	1		T290	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T249	1		T291	1		T292	1
auto[TlIntgErrData]	partial	auto[0]	32	1		T102	3		T209	1		T210	4
auto[TlIntgErrData]	partial	auto[1]	32	1		T102	1		T209	3		T249	2
auto[TlIntgErrData]	full_word	auto[0]	2	1		T293	1		T294	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	3	1		T249	1		T286	1		T295	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1		T102	3		T209	1		T210	2
auto[TlIntgErrBoth]	partial	auto[1]	50	1		T102	1		T210	5		T249	4
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T287	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T210	1		T287	1		T295	1