Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.91	100.00	67.63			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_rxfifo	90.62	100.00	62.50			100.00	100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo	90.62	100.00	62.50			100.00	100.00
tb.dut.usbdev_avsetupfifo	91.07	100.00	64.29			100.00	100.00
tb.dut.usbdev_avoutfifo	91.07	100.00	64.29			100.00	100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo	92.19	100.00	68.75			100.00	100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo	93.75	100.00	75.00			100.00	100.00
tb.dut.u_reg.u_socket.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.usbdev_rxfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.62	100.00	62.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.47	95.12	77.78			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.68	93.83	68.66	94.27		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	86.51	92.59	90.00			76.92

---

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.62	100.00	62.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.64	95.00	72.22			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.37	98.55	78.63			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

---

Module Instance : tb.dut.usbdev_avsetupfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.07	100.00	64.29			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	100.00	85.29			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.68	93.83	68.66	94.27		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.usbdev_avoutfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.07	100.00	64.29			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	100.00	85.29			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.68	93.83	68.66	94.27		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.37	98.55	78.63			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

---

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.32	95.00	77.27			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.37	98.55	78.63			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

---

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=0,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
91.07	100.00

tb.dut.usbdev_avsetupfifo

SCORE	LINE
91.07	100.00

tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.62	100.00

tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.fifo_h.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.fifo_h.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
92.19	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

SCORE	LINE
90.62	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.75	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.75	75.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T16,T88
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Not Covered
1	1	Covered	T9,T14,T16

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T9,T14,T16

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T14,T16,T88
1	1	0	Not Covered
1	1	1	Covered	T9,T14,T16

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T9,T14,T16

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T4,T5
1	1	Covered	T9,T14,T16

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T14,T16,T88
1	0	Covered	T9,T14,T16
1	1	Covered	T3,T4,T5

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T9,T14,T16
1	Covered	T3,T4,T5

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=0,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
91.07	64.29

tb.dut.usbdev_avsetupfifo

SCORE	COND
91.07	64.29

tb.dut.usbdev_avoutfifo

	Total	Covered	Percent
Conditions	14	9	64.29
Logical	14	9	64.29
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T62
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Not Covered
1	1	Covered	T3,T4,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T3,T9,T14

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 + Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
90.62	62.50

tb.dut.usbdev_rxfifo

SCORE	COND
92.19	68.75

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T14,T16
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Not Covered
1	1	Covered	T3,T9,T14

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T9,T14

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T9,T14
1	1	0	Not Covered
1	1	1	Covered	T9,T14,T43

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T3,T9,T14
1	Covered	T3,T4,T5

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
90.62	62.50

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T14,T16
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Not Covered
1	1	Covered	T9,T14,T16

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T9,T14,T16

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T9,T14,T16

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T9,T14,T16
1	Covered	T3,T4,T5

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=0,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
91.07	100.00

tb.dut.usbdev_avsetupfifo

SCORE	BRANCH
91.07	100.00

tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T4,T5
0	1	Covered	T3,T4,T5
0	0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T3,T4,T5

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
93.75	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T14,T16
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T9,T14,T16

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T4,T5
0	1	Covered	T3,T4,T5
0	0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T9,T14,T16
0	Covered	T3,T4,T5

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 + Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
90.62	100.00

tb.dut.usbdev_rxfifo

SCORE	BRANCH
92.19	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

SCORE	BRANCH
90.62	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T3,T9,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T4,T5
0	1	Covered	T3,T4,T5
0	0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T9,T14
0	Covered	T3,T4,T5

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	452868984	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	2147483647	447089704	0	0
gen_passthru_fifo.paramCheckPass	9180	9180	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	452868984	0	0
T3	2437722	402118	0	0
T4	62391	11394	0	0
T5	33341	5755	0	0
T9	4843848	402019	0	0
T10	4821672	56	0	0
T14	4832448	401282	0	0
T16	0	45128	0	0
T19	0	1856	0	0
T20	0	850	0	0
T21	4825800	36	0	0
T22	4823844	62	0	0
T23	4841808	400841	0	0
T24	4846632	401360	0	0
T33	2024135	403950	0	0
T34	2024055	403594	0	0
T36	0	285	0	0
T43	2419236	400801	0	0
T88	0	124	0	0
T89	0	10	0	0
T90	0	80	0	0
T91	0	80	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T3	4875444	4874580	0	0
T4	106956	106068	0	0
T5	57156	55956	0	0
T9	4843848	4842732	0	0
T10	4821672	4819884	0	0
T14	4832448	4831488	0	0
T21	4825800	4823892	0	0
T22	4823844	4822200	0	0
T23	4841808	4840920	0	0
T24	4846632	4845468	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T3	4875444	4874580	0	0
T4	106956	106068	0	0
T5	57156	55956	0	0
T9	4843848	4842732	0	0
T10	4821672	4819884	0	0
T14	4832448	4831488	0	0
T21	4825800	4823892	0	0
T22	4823844	4822200	0	0
T23	4841808	4840920	0	0
T24	4846632	4845468	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T3	4875444	4874580	0	0
T4	106956	106068	0	0
T5	57156	55956	0	0
T9	4843848	4842732	0	0
T10	4821672	4819884	0	0
T14	4832448	4831488	0	0
T21	4825800	4823892	0	0
T22	4823844	4822200	0	0
T23	4841808	4840920	0	0
T24	4846632	4845468	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	447089704	0	0
T3	812574	402062	0	0
T4	26739	13827	0	0
T5	14289	6914	0	0
T9	2421924	401927	0	0
T10	2410836	0	0	0
T14	2416224	401142	0	0
T16	0	26596	0	0
T19	0	1187	0	0
T20	0	510	0	0
T21	2412900	0	0	0
T22	2411922	0	0	0
T23	2420904	400745	0	0
T24	2423316	401304	0	0
T30	0	402340	0	0
T31	0	400434	0	0
T33	1214481	403950	0	0
T34	1214433	403594	0	0
T36	0	171	0	0
T43	1612824	400801	0	0
T62	0	2580	0	0
T88	0	79	0	0
T89	0	6	0	0
T90	0	48	0	0
T91	0	48	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	9180	9180	0	0
T3	6	6	0	0
T4	6	6	0	0
T5	6	6	0	0
T9	6	6	0	0
T10	6	6	0	0
T14	6	6	0	0
T21	6	6	0	0
T22	6	6	0	0
T23	6	6	0	0
T24	6	6	0	0

Line Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Not Covered
1	1	Covered	T3,T9,T14

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T9,T14

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T9,T14
1	1	0	Not Covered
1	1	1	Covered	T9,T14,T43

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T3,T9,T14
1	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T3,T9,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T4,T5
0	1	Covered	T3,T4,T5
0	0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T9,T14
0	Covered	T3,T4,T5

---

Assert Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	539765567	2245819	0	0
DepthKnown_A	539765567	539641887	0	0
RvalidKnown_A	539765567	539641887	0	0
WreadyKnown_A	539765567	539641887	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	539765567	2245819	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539765567	2245819	0	0
T3	406287	2973	0	0
T4	8913	0	0	0
T5	4763	0	0	0
T9	403654	100	0	0
T10	401806	0	0	0
T14	402704	123	0	0
T16	0	17210	0	0
T21	402150	0	0	0
T22	401987	0	0	0
T23	403484	2016	0	0
T24	403886	2126	0	0
T33	0	124	0	0
T34	0	122	0	0
T43	0	98	0	0
T44	0	1276	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539765567	539641887	0	0
T3	406287	406215	0	0
T4	8913	8839	0	0
T5	4763	4663	0	0
T9	403654	403561	0	0
T10	401806	401657	0	0
T14	402704	402624	0	0
T21	402150	401991	0	0
T22	401987	401850	0	0
T23	403484	403410	0	0
T24	403886	403789	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539765567	539641887	0	0
T3	406287	406215	0	0
T4	8913	8839	0	0
T5	4763	4663	0	0
T9	403654	403561	0	0
T10	401806	401657	0	0
T14	402704	402624	0	0
T21	402150	401991	0	0
T22	401987	401850	0	0
T23	403484	403410	0	0
T24	403886	403789	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539765567	539641887	0	0
T3	406287	406215	0	0
T4	8913	8839	0	0
T5	4763	4663	0	0
T9	403654	403561	0	0
T10	401806	401657	0	0
T14	402704	402624	0	0
T21	402150	401991	0	0
T22	401987	401850	0	0
T23	403484	403410	0	0
T24	403886	403789	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	539765567	2245819	0	0
T3	406287	2973	0	0
T4	8913	0	0	0
T5	4763	0	0	0
T9	403654	100	0	0
T10	401806	0	0	0
T14	402704	123	0	0
T16	0	17210	0	0
T21	402150	0	0	0
T22	401987	0	0	0
T23	403484	2016	0	0
T24	403886	2126	0	0
T33	0	124	0	0
T34	0	122	0	0
T43	0	98	0	0
T44	0	1276	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T14,T16
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Not Covered
1	1	Covered	T9,T14,T16

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T9,T14,T16

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T9,T14,T16

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T9,T14,T16
1	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T9,T14,T16

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T4,T5
0	1	Covered	T3,T4,T5
0	0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T9,T14,T16
0	Covered	T3,T4,T5

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	539765567	200016	0	0
DepthKnown_A	539765567	539641887	0	0
RvalidKnown_A	539765567	539641887	0	0
WreadyKnown_A	539765567	539641887	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	539765567	200016	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539765567	200016	0	0
T9	403654	13	0	0
T10	401806	0	0	0
T14	402704	6	0	0
T16	0	2064	0	0
T19	0	151	0	0
T20	0	170	0	0
T21	402150	0	0	0
T22	401987	0	0	0
T23	403484	0	0	0
T24	403886	0	0	0
T33	404827	0	0	0
T34	404811	0	0	0
T36	0	57	0	0
T43	403206	0	0	0
T88	0	11	0	0
T89	0	2	0	0
T90	0	16	0	0
T91	0	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539765567	539641887	0	0
T3	406287	406215	0	0
T4	8913	8839	0	0
T5	4763	4663	0	0
T9	403654	403561	0	0
T10	401806	401657	0	0
T14	402704	402624	0	0
T21	402150	401991	0	0
T22	401987	401850	0	0
T23	403484	403410	0	0
T24	403886	403789	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539765567	539641887	0	0
T3	406287	406215	0	0
T4	8913	8839	0	0
T5	4763	4663	0	0
T9	403654	403561	0	0
T10	401806	401657	0	0
T14	402704	402624	0	0
T21	402150	401991	0	0
T22	401987	401850	0	0
T23	403484	403410	0	0
T24	403886	403789	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539765567	539641887	0	0
T3	406287	406215	0	0
T4	8913	8839	0	0
T5	4763	4663	0	0
T9	403654	403561	0	0
T10	401806	401657	0	0
T14	402704	402624	0	0
T21	402150	401991	0	0
T22	401987	401850	0	0
T23	403484	403410	0	0
T24	403886	403789	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	539765567	200016	0	0
T9	403654	13	0	0
T10	401806	0	0	0
T14	402704	6	0	0
T16	0	2064	0	0
T19	0	151	0	0
T20	0	170	0	0
T21	402150	0	0	0
T22	401987	0	0	0
T23	403484	0	0	0
T24	403886	0	0	0
T33	404827	0	0	0
T34	404811	0	0	0
T36	0	57	0	0
T43	403206	0	0	0
T88	0	11	0	0
T89	0	2	0	0
T90	0	16	0	0
T91	0	16	0	0

Line Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Covered	Percent
Conditions	14	9	64.29
Logical	14	9	64.29
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T62
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Not Covered
1	1	Covered	T4,T5,T62

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T62

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T62
1	1	0	Not Covered
1	1	1	Covered	T30,T31,T32

---

Branch Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T4,T5
0	1	Covered	T3,T4,T5
0	0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T62
0	Covered	T3,T4,T5

---

Assert Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	539765567	60578896	0	0
DepthKnown_A	539765567	539641887	0	0
RvalidKnown_A	539765567	539641887	0	0
WreadyKnown_A	539765567	539641887	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	539765567	60578896	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539765567	60578896	0	0
T4	8913	6753	0	0
T5	4763	3047	0	0
T9	403654	0	0	0
T10	401806	0	0	0
T14	402704	0	0	0
T21	402150	0	0	0
T22	401987	0	0	0
T23	403484	0	0	0
T24	403886	0	0	0
T30	0	402340	0	0
T31	0	400434	0	0
T32	0	401888	0	0
T43	403206	0	0	0
T60	0	400818	0	0
T62	0	2580	0	0
T92	0	4157	0	0
T93	0	2621	0	0
T94	0	2616	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539765567	539641887	0	0
T3	406287	406215	0	0
T4	8913	8839	0	0
T5	4763	4663	0	0
T9	403654	403561	0	0
T10	401806	401657	0	0
T14	402704	402624	0	0
T21	402150	401991	0	0
T22	401987	401850	0	0
T23	403484	403410	0	0
T24	403886	403789	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539765567	539641887	0	0
T3	406287	406215	0	0
T4	8913	8839	0	0
T5	4763	4663	0	0
T9	403654	403561	0	0
T10	401806	401657	0	0
T14	402704	402624	0	0
T21	402150	401991	0	0
T22	401987	401850	0	0
T23	403484	403410	0	0
T24	403886	403789	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539765567	539641887	0	0
T3	406287	406215	0	0
T4	8913	8839	0	0
T5	4763	4663	0	0
T9	403654	403561	0	0
T10	401806	401657	0	0
T14	402704	402624	0	0
T21	402150	401991	0	0
T22	401987	401850	0	0
T23	403484	403410	0	0
T24	403886	403789	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	539765567	60578896	0	0
T4	8913	6753	0	0
T5	4763	3047	0	0
T9	403654	0	0	0
T10	401806	0	0	0
T14	402704	0	0	0
T21	402150	0	0	0
T22	401987	0	0	0
T23	403484	0	0	0
T24	403886	0	0	0
T30	0	402340	0	0
T31	0	400434	0	0
T32	0	401888	0	0
T43	403206	0	0	0
T60	0	400818	0	0
T62	0	2580	0	0
T92	0	4157	0	0
T93	0	2621	0	0
T94	0	2616	0	0

Line Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Covered	Percent
Conditions	14	9	64.29
Logical	14	9	64.29
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T62
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Not Covered
1	1	Covered	T3,T4,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T3,T9,T14

---

Branch Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T4,T5
0	1	Covered	T3,T4,T5
0	0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T3,T4,T5

---

Assert Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	539765567	383189421	0	0
DepthKnown_A	539765567	539641887	0	0
RvalidKnown_A	539765567	539641887	0	0
WreadyKnown_A	539765567	539641887	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	539765567	383189421	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539765567	383189421	0	0
T3	406287	402062	0	0
T4	8913	7074	0	0
T5	4763	3867	0	0
T9	403654	401888	0	0
T10	401806	0	0	0
T14	402704	401100	0	0
T21	402150	0	0	0
T22	401987	0	0	0
T23	403484	400745	0	0
T24	403886	401304	0	0
T33	0	403950	0	0
T34	0	403594	0	0
T43	0	400801	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539765567	539641887	0	0
T3	406287	406215	0	0
T4	8913	8839	0	0
T5	4763	4663	0	0
T9	403654	403561	0	0
T10	401806	401657	0	0
T14	402704	402624	0	0
T21	402150	401991	0	0
T22	401987	401850	0	0
T23	403484	403410	0	0
T24	403886	403789	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539765567	539641887	0	0
T3	406287	406215	0	0
T4	8913	8839	0	0
T5	4763	4663	0	0
T9	403654	403561	0	0
T10	401806	401657	0	0
T14	402704	402624	0	0
T21	402150	401991	0	0
T22	401987	401850	0	0
T23	403484	403410	0	0
T24	403886	403789	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539765567	539641887	0	0
T3	406287	406215	0	0
T4	8913	8839	0	0
T5	4763	4663	0	0
T9	403654	403561	0	0
T10	401806	401657	0	0
T14	402704	402624	0	0
T21	402150	401991	0	0
T22	401987	401850	0	0
T23	403484	403410	0	0
T24	403886	403789	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	539765567	383189421	0	0
T3	406287	402062	0	0
T4	8913	7074	0	0
T5	4763	3867	0	0
T9	403654	401888	0	0
T10	401806	0	0	0
T14	402704	401100	0	0
T21	402150	0	0	0
T22	401987	0	0	0
T23	403484	400745	0	0
T24	403886	401304	0	0
T33	0	403950	0	0
T34	0	403594	0	0
T43	0	400801	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T14,T16
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Not Covered
1	1	Covered	T9,T14,T16

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T9,T14,T16

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T14,T16,T88
1	1	0	Not Covered
1	1	1	Covered	T9,T14,T16

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T9,T14,T16
1	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T9,T14,T16

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T4,T5
0	1	Covered	T3,T4,T5
0	0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T9,T14,T16
0	Covered	T3,T4,T5

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	539765567	544856	0	0
DepthKnown_A	539765567	539641887	0	0
RvalidKnown_A	539765567	539641887	0	0
WreadyKnown_A	539765567	539641887	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	539765567	544856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539765567	544856	0	0
T9	403654	13	0	0
T10	401806	0	0	0
T14	402704	18	0	0
T16	0	15193	0	0
T19	0	518	0	0
T20	0	170	0	0
T21	402150	0	0	0
T22	401987	0	0	0
T23	403484	0	0	0
T24	403886	0	0	0
T33	404827	0	0	0
T34	404811	0	0	0
T36	0	57	0	0
T43	403206	0	0	0
T88	0	34	0	0
T89	0	2	0	0
T90	0	16	0	0
T91	0	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539765567	539641887	0	0
T3	406287	406215	0	0
T4	8913	8839	0	0
T5	4763	4663	0	0
T9	403654	403561	0	0
T10	401806	401657	0	0
T14	402704	402624	0	0
T21	402150	401991	0	0
T22	401987	401850	0	0
T23	403484	403410	0	0
T24	403886	403789	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539765567	539641887	0	0
T3	406287	406215	0	0
T4	8913	8839	0	0
T5	4763	4663	0	0
T9	403654	403561	0	0
T10	401806	401657	0	0
T14	402704	402624	0	0
T21	402150	401991	0	0
T22	401987	401850	0	0
T23	403484	403410	0	0
T24	403886	403789	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539765567	539641887	0	0
T3	406287	406215	0	0
T4	8913	8839	0	0
T5	4763	4663	0	0
T9	403654	403561	0	0
T10	401806	401657	0	0
T14	402704	402624	0	0
T21	402150	401991	0	0
T22	401987	401850	0	0
T23	403484	403410	0	0
T24	403886	403789	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	539765567	544856	0	0
T9	403654	13	0	0
T10	401806	0	0	0
T14	402704	18	0	0
T16	0	15193	0	0
T19	0	518	0	0
T20	0	170	0	0
T21	402150	0	0	0
T22	401987	0	0	0
T23	403484	0	0	0
T24	403886	0	0	0
T33	404827	0	0	0
T34	404811	0	0	0
T36	0	57	0	0
T43	403206	0	0	0
T88	0	34	0	0
T89	0	2	0	0
T90	0	16	0	0
T91	0	16	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T16,T88
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Not Covered
1	1	Covered	T9,T14,T16

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T9,T14,T16

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T14,T16,T88
1	1	0	Not Covered
1	1	1	Covered	T9,T14,T16

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T9,T14,T16

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T4,T5
1	1	Covered	T9,T14,T16

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T14,T16,T88
1	0	Covered	T9,T14,T16
1	1	Covered	T3,T4,T5

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T9,T14,T16
1	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T14,T16
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T9,T14,T16

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T4,T5
0	1	Covered	T3,T4,T5
0	0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T9,T14,T16
0	Covered	T3,T4,T5

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	539765567	330696	0	0
DepthKnown_A	539765567	539641887	0	0
RvalidKnown_A	539765567	539641887	0	0
WreadyKnown_A	539765567	539641887	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	539765567	330696	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539765567	330696	0	0
T9	403654	13	0	0
T10	401806	0	0	0
T14	402704	18	0	0
T16	0	9339	0	0
T19	0	518	0	0
T20	0	170	0	0
T21	402150	0	0	0
T22	401987	0	0	0
T23	403484	0	0	0
T24	403886	0	0	0
T33	404827	0	0	0
T34	404811	0	0	0
T36	0	57	0	0
T43	403206	0	0	0
T88	0	34	0	0
T89	0	2	0	0
T90	0	16	0	0
T91	0	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539765567	539641887	0	0
T3	406287	406215	0	0
T4	8913	8839	0	0
T5	4763	4663	0	0
T9	403654	403561	0	0
T10	401806	401657	0	0
T14	402704	402624	0	0
T21	402150	401991	0	0
T22	401987	401850	0	0
T23	403484	403410	0	0
T24	403886	403789	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539765567	539641887	0	0
T3	406287	406215	0	0
T4	8913	8839	0	0
T5	4763	4663	0	0
T9	403654	403561	0	0
T10	401806	401657	0	0
T14	402704	402624	0	0
T21	402150	401991	0	0
T22	401987	401850	0	0
T23	403484	403410	0	0
T24	403886	403789	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539765567	539641887	0	0
T3	406287	406215	0	0
T4	8913	8839	0	0
T5	4763	4663	0	0
T9	403654	403561	0	0
T10	401806	401657	0	0
T14	402704	402624	0	0
T21	402150	401991	0	0
T22	401987	401850	0	0
T23	403484	403410	0	0
T24	403886	403789	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	539765567	330696	0	0
T9	403654	13	0	0
T10	401806	0	0	0
T14	402704	18	0	0
T16	0	9339	0	0
T19	0	518	0	0
T20	0	170	0	0
T21	402150	0	0	0
T22	401987	0	0	0
T23	403484	0	0	0
T24	403886	0	0	0
T33	404827	0	0	0
T34	404811	0	0	0
T36	0	57	0	0
T43	403206	0	0	0
T88	0	34	0	0
T89	0	2	0	0
T90	0	16	0	0
T91	0	16	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	541172410	1259750	0	0
DepthKnown_A	541172410	541004114	0	0
RvalidKnown_A	541172410	541004114	0	0
WreadyKnown_A	541172410	541004114	0	0
gen_passthru_fifo.paramCheckPass	1530	1530	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541172410	1259750	0	0
T3	406287	14	0	0
T4	8913	1080	0	0
T5	4763	472	0	0
T9	403654	23	0	0
T10	401806	9	0	0
T14	402704	16	0	0
T21	402150	9	0	0
T22	401987	9	0	0
T23	403484	10	0	0
T24	403886	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541172410	541004114	0	0
T3	406287	406215	0	0
T4	8913	8839	0	0
T5	4763	4663	0	0
T9	403654	403561	0	0
T10	401806	401657	0	0
T14	402704	402624	0	0
T21	402150	401991	0	0
T22	401987	401850	0	0
T23	403484	403410	0	0
T24	403886	403789	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541172410	541004114	0	0
T3	406287	406215	0	0
T4	8913	8839	0	0
T5	4763	4663	0	0
T9	403654	403561	0	0
T10	401806	401657	0	0
T14	402704	402624	0	0
T21	402150	401991	0	0
T22	401987	401850	0	0
T23	403484	403410	0	0
T24	403886	403789	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541172410	541004114	0	0
T3	406287	406215	0	0
T4	8913	8839	0	0
T5	4763	4663	0	0
T9	403654	403561	0	0
T10	401806	401657	0	0
T14	402704	402624	0	0
T21	402150	401991	0	0
T22	401987	401850	0	0
T23	403484	403410	0	0
T24	403886	403789	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1530	1530	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T14	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	541172410	1659719	0	0
DepthKnown_A	541172410	541004114	0	0
RvalidKnown_A	541172410	541004114	0	0
WreadyKnown_A	541172410	541004114	0	0
gen_passthru_fifo.paramCheckPass	1530	1530	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541172410	1659719	0	0
T3	406287	14	0	0
T4	8913	1080	0	0
T5	4763	472	0	0
T9	403654	23	0	0
T10	401806	19	0	0
T14	402704	54	0	0
T21	402150	9	0	0
T22	401987	22	0	0
T23	403484	38	0	0
T24	403886	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541172410	541004114	0	0
T3	406287	406215	0	0
T4	8913	8839	0	0
T5	4763	4663	0	0
T9	403654	403561	0	0
T10	401806	401657	0	0
T14	402704	402624	0	0
T21	402150	401991	0	0
T22	401987	401850	0	0
T23	403484	403410	0	0
T24	403886	403789	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541172410	541004114	0	0
T3	406287	406215	0	0
T4	8913	8839	0	0
T5	4763	4663	0	0
T9	403654	403561	0	0
T10	401806	401657	0	0
T14	402704	402624	0	0
T21	402150	401991	0	0
T22	401987	401850	0	0
T23	403484	403410	0	0
T24	403886	403789	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541172410	541004114	0	0
T3	406287	406215	0	0
T4	8913	8839	0	0
T5	4763	4663	0	0
T9	403654	403561	0	0
T10	401806	401657	0	0
T14	402704	402624	0	0
T21	402150	401991	0	0
T22	401987	401850	0	0
T23	403484	403410	0	0
T24	403886	403789	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1530	1530	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T14	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	541172410	367874	0	0
DepthKnown_A	541172410	541004114	0	0
RvalidKnown_A	541172410	541004114	0	0
WreadyKnown_A	541172410	541004114	0	0
gen_passthru_fifo.paramCheckPass	1530	1530	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541172410	367874	0	0
T9	403654	13	0	0
T10	401806	0	0	0
T14	402704	6	0	0
T16	0	3339	0	0
T19	0	151	0	0
T20	0	170	0	0
T21	402150	0	0	0
T22	401987	0	0	0
T23	403484	0	0	0
T24	403886	0	0	0
T33	404827	0	0	0
T34	404811	0	0	0
T36	0	57	0	0
T43	403206	0	0	0
T88	0	11	0	0
T89	0	2	0	0
T90	0	16	0	0
T91	0	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541172410	541004114	0	0
T3	406287	406215	0	0
T4	8913	8839	0	0
T5	4763	4663	0	0
T9	403654	403561	0	0
T10	401806	401657	0	0
T14	402704	402624	0	0
T21	402150	401991	0	0
T22	401987	401850	0	0
T23	403484	403410	0	0
T24	403886	403789	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541172410	541004114	0	0
T3	406287	406215	0	0
T4	8913	8839	0	0
T5	4763	4663	0	0
T9	403654	403561	0	0
T10	401806	401657	0	0
T14	402704	402624	0	0
T21	402150	401991	0	0
T22	401987	401850	0	0
T23	403484	403410	0	0
T24	403886	403789	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541172410	541004114	0	0
T3	406287	406215	0	0
T4	8913	8839	0	0
T5	4763	4663	0	0
T9	403654	403561	0	0
T10	401806	401657	0	0
T14	402704	402624	0	0
T21	402150	401991	0	0
T22	401987	401850	0	0
T23	403484	403410	0	0
T24	403886	403789	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1530	1530	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T14	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	541172410	593205	0	0
DepthKnown_A	541172410	541004114	0	0
RvalidKnown_A	541172410	541004114	0	0
WreadyKnown_A	541172410	541004114	0	0
gen_passthru_fifo.paramCheckPass	1530	1530	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541172410	593205	0	0
T9	403654	13	0	0
T10	401806	0	0	0
T14	402704	18	0	0
T16	0	15193	0	0
T19	0	518	0	0
T20	0	170	0	0
T21	402150	0	0	0
T22	401987	0	0	0
T23	403484	0	0	0
T24	403886	0	0	0
T33	404827	0	0	0
T34	404811	0	0	0
T36	0	57	0	0
T43	403206	0	0	0
T88	0	34	0	0
T89	0	2	0	0
T90	0	16	0	0
T91	0	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541172410	541004114	0	0
T3	406287	406215	0	0
T4	8913	8839	0	0
T5	4763	4663	0	0
T9	403654	403561	0	0
T10	401806	401657	0	0
T14	402704	402624	0	0
T21	402150	401991	0	0
T22	401987	401850	0	0
T23	403484	403410	0	0
T24	403886	403789	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541172410	541004114	0	0
T3	406287	406215	0	0
T4	8913	8839	0	0
T5	4763	4663	0	0
T9	403654	403561	0	0
T10	401806	401657	0	0
T14	402704	402624	0	0
T21	402150	401991	0	0
T22	401987	401850	0	0
T23	403484	403410	0	0
T24	403886	403789	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541172410	541004114	0	0
T3	406287	406215	0	0
T4	8913	8839	0	0
T5	4763	4663	0	0
T9	403654	403561	0	0
T10	401806	401657	0	0
T14	402704	402624	0	0
T21	402150	401991	0	0
T22	401987	401850	0	0
T23	403484	403410	0	0
T24	403886	403789	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1530	1530	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T14	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	541172410	832218	0	0
DepthKnown_A	541172410	541004114	0	0
RvalidKnown_A	541172410	541004114	0	0
WreadyKnown_A	541172410	541004114	0	0
gen_passthru_fifo.paramCheckPass	1530	1530	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541172410	832218	0	0
T3	406287	14	0	0
T4	8913	1080	0	0
T5	4763	472	0	0
T9	403654	10	0	0
T10	401806	9	0	0
T14	402704	10	0	0
T21	402150	9	0	0
T22	401987	9	0	0
T23	403484	10	0	0
T24	403886	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541172410	541004114	0	0
T3	406287	406215	0	0
T4	8913	8839	0	0
T5	4763	4663	0	0
T9	403654	403561	0	0
T10	401806	401657	0	0
T14	402704	402624	0	0
T21	402150	401991	0	0
T22	401987	401850	0	0
T23	403484	403410	0	0
T24	403886	403789	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541172410	541004114	0	0
T3	406287	406215	0	0
T4	8913	8839	0	0
T5	4763	4663	0	0
T9	403654	403561	0	0
T10	401806	401657	0	0
T14	402704	402624	0	0
T21	402150	401991	0	0
T22	401987	401850	0	0
T23	403484	403410	0	0
T24	403886	403789	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541172410	541004114	0	0
T3	406287	406215	0	0
T4	8913	8839	0	0
T5	4763	4663	0	0
T9	403654	403561	0	0
T10	401806	401657	0	0
T14	402704	402624	0	0
T21	402150	401991	0	0
T22	401987	401850	0	0
T23	403484	403410	0	0
T24	403886	403789	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1530	1530	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T14	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	541172410	1066514	0	0
DepthKnown_A	541172410	541004114	0	0
RvalidKnown_A	541172410	541004114	0	0
WreadyKnown_A	541172410	541004114	0	0
gen_passthru_fifo.paramCheckPass	1530	1530	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541172410	1066514	0	0
T3	406287	14	0	0
T4	8913	1080	0	0
T5	4763	472	0	0
T9	403654	10	0	0
T10	401806	19	0	0
T14	402704	36	0	0
T21	402150	9	0	0
T22	401987	22	0	0
T23	403484	38	0	0
T24	403886	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541172410	541004114	0	0
T3	406287	406215	0	0
T4	8913	8839	0	0
T5	4763	4663	0	0
T9	403654	403561	0	0
T10	401806	401657	0	0
T14	402704	402624	0	0
T21	402150	401991	0	0
T22	401987	401850	0	0
T23	403484	403410	0	0
T24	403886	403789	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541172410	541004114	0	0
T3	406287	406215	0	0
T4	8913	8839	0	0
T5	4763	4663	0	0
T9	403654	403561	0	0
T10	401806	401657	0	0
T14	402704	402624	0	0
T21	402150	401991	0	0
T22	401987	401850	0	0
T23	403484	403410	0	0
T24	403886	403789	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541172410	541004114	0	0
T3	406287	406215	0	0
T4	8913	8839	0	0
T5	4763	4663	0	0
T9	403654	403561	0	0
T10	401806	401657	0	0
T14	402704	402624	0	0
T21	402150	401991	0	0
T22	401987	401850	0	0
T23	403484	403410	0	0
T24	403886	403789	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1530	1530	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T14	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0