Module Definition
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Module : tlul_adapter_sram
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.37 98.55 78.63 92.31 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_no_stubbed_memory.u_tlul2sram 92.37 98.55 78.63 92.31 100.00



Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.37 98.55 78.63 92.31 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.91 86.78 75.75 81.11 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
89.68 93.83 68.66 94.27 91.67 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_err 67.62 76.92 68.57 25.00 100.00
u_reqfifo 88.33 95.00 75.00 83.33 100.00
u_rsp_gen 91.67 83.33 100.00
u_rspfifo 89.32 95.00 77.27 85.00 100.00
u_sram_byte 100.00 100.00
u_sramreqfifo 87.64 95.00 72.22 83.33 100.00
u_tlul_data_integ_enc_data 0.00 0.00
u_tlul_data_integ_enc_instr 0.00 0.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : tlul_adapter_sram
Line No.TotalCoveredPercent
TOTAL696898.55
ALWAYS9433100.00
CONT_ASSIGN10311100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN11511100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN15211100.00
CONT_ASSIGN22411100.00
CONT_ASSIGN22511100.00
CONT_ASSIGN22611100.00
ALWAYS2318787.50
ALWAYS25166100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26911100.00
CONT_ASSIGN28811100.00
CONT_ASSIGN29311100.00
CONT_ASSIGN29911100.00
CONT_ASSIGN31111100.00
ALWAYS31433100.00
CONT_ASSIGN32111100.00
CONT_ASSIGN34111100.00
CONT_ASSIGN34211100.00
CONT_ASSIGN34311100.00
CONT_ASSIGN34411100.00
ALWAYS37466100.00
ALWAYS38655100.00
CONT_ASSIGN40111100.00
CONT_ASSIGN40211100.00
CONT_ASSIGN40311100.00
CONT_ASSIGN40711100.00
CONT_ASSIGN40811100.00
CONT_ASSIGN41011100.00
CONT_ASSIGN41111100.00
CONT_ASSIGN41811100.00
CONT_ASSIGN42111100.00
CONT_ASSIGN42511100.00
CONT_ASSIGN42611100.00
CONT_ASSIGN42811100.00
CONT_ASSIGN43511100.00
ALWAYS45333100.00
CONT_ASSIGN45911100.00
CONT_ASSIGN46211100.00
CONT_ASSIGN46711100.00
CONT_ASSIGN47200
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
95 1 1
96 1 1
97 unreachable
MISSING_ELSE
103 1 1
108 1 1
115 1 1
140 1 1
152 1 1
224 1 1
225 1 1
226 1 1
231 1 1
233 1 1
234 1 1
236 0 1
237 1 1
238 1 1
241 1 1
244 1 1
251 1 1
253 1 1
254 1 1
255 1 1
257 1 1
260 1 1
265 1 1
269 1 1
288 1 1
293 1 1
299 1 1
311 1 1
314 1 1
315 1 1
317 1 1
321 1 1
341 1 1
342 1 1
343 1 1
344 1 1
374 1 1
375 1 1
377 1 1
378 1 1
379 1 1
380 1 1
MISSING_ELSE
386 1 1
387 1 1
389 1 1
390 1 1
391 1 1
MISSING_ELSE
401 1 1
402 1 1
403 1 1
407 1 1
408 1 1
410 1 1
411 1 1
418 1 1
421 1 1
425 1 1
426 1 1
428 1 1
435 1 1
453 1 1
454 1 1
455 1 1
459 1 1
462 1 1
467 1 1
472 unreachable


Cond Coverage for Module : tlul_adapter_sram
TotalCoveredPercent
Conditions1179278.63
Logical1179278.63
Non-Logical00
Event00

 LINE       96
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT3,T4,T5
01Unreachable
10Unreachable

 LINE       103
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT3,T4,T5
001Not Covered
010Unreachable
100Unreachable

 LINE       108
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT3,T4,T5
1CoveredT3,T4,T5

 LINE       108
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT3,T4,T5
01CoveredT3,T4,T5
10CoveredT3,T4,T5

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT3,T4,T5
1CoveredT3,T4,T5

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT3,T4,T5
1CoveredT3,T4,T5

 LINE       108
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT3,T4,T5
01CoveredT5,T19,T20
10CoveredT3,T4,T5

 LINE       108
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT3,T4,T5
1CoveredT3,T4,T5

 LINE       108
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT3,T4,T5
1CoveredT3,T4,T5

 LINE       140
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT9,T14,T16
000001Unreachable
000010CoveredT3,T4,T5
000100Not Covered
001000Unreachable
010000Unreachable
100000Not Covered

 LINE       224
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT3,T4,T5
10CoveredT9,T14,T16
11CoveredT9,T14,T16

 LINE       225
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT3,T4,T5
10CoveredT14,T16,T88
11CoveredT9,T14,T16

 LINE       226
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01CoveredT3,T4,T5
10CoveredT16,T95,T96
11CoveredT9,T14,T16

 LINE       237
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT16,T17,T97
1CoveredT9,T14,T16

 LINE       254
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT16,T17,T97
1CoveredT9,T14,T16

 LINE       255
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00CoveredT9,T14,T16
01Not Covered
10Not Covered

 LINE       265
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101Not Covered
1110Not Covered
1111CoveredT9,T14,T16

 LINE       265
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT3,T4,T5
1CoveredT9,T14,T16

 LINE       293
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT3,T4,T5
1CoveredT9,T14,T16

 LINE       293
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT3,T4,T5
10Not Covered
11CoveredT9,T14,T16

 LINE       299
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT3,T4,T5
1Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01Not Covered
10CoveredT9,T14,T16
11Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT3,T4,T5
1CoveredT9,T14,T16

 LINE       311
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------
-1--2--3-StatusTests
011CoveredT9,T14,T16
101CoveredT3,T4,T5
110Not Covered
111Not Covered

 LINE       321
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT3,T4,T5
1CoveredT16,T17,T97

 LINE       321
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT3,T4,T5
10CoveredT9,T14,T16
11CoveredT16,T17,T97

 LINE       321
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT3,T4,T5
1CoveredT3,T4,T5

 LINE       321
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT3,T4,T5
1CoveredT9,T14,T16

 LINE       321
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT3,T4,T5
1CoveredT9,T14,T16

 LINE       321
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT9,T14,T16
11Not Covered

 LINE       321
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready)
             -------------1------------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT3,T9,T14
101CoveredT14,T16,T88
110Not Covered
111CoveredT3,T4,T5

 LINE       321
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------
-1--2-StatusTests
00CoveredT3,T9,T14
01Not Covered
10CoveredT3,T4,T5

 LINE       341
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT9,T14,T16
110Not Covered
111CoveredT9,T14,T16

 LINE       343
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT3,T4,T5
10CoveredT9,T14,T16
11CoveredT16,T17,T97

 LINE       344
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT3,T4,T5
1CoveredT9,T14,T16

 LINE       380
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT9,T14,T16
1CoveredT16,T17,T97

 LINE       380
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10CoveredT9,T14,T16
11CoveredT16,T17,T97

 LINE       403
 EXPRESSION (((|wmask_intg)) & ((|wdata_intg)))
             -------1-------   -------2-------
-1--2-StatusTests
01Not Covered
10CoveredT16,T19,T36
11CoveredT9,T14,T16

 LINE       411
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT3,T4,T5
1CoveredT3,T4,T5

 LINE       411
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT3,T4,T5
1CoveredT3,T4,T5

 LINE       425
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT3,T4,T5
10CoveredT16,T17,T97
11CoveredT9,T14,T16

 LINE       428
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT14,T16,T88
10Not Covered
11CoveredT9,T14,T16

 LINE       467
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT3,T4,T5
1CoveredT9,T14,T16

 LINE       467
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT3,T4,T5
10Not Covered
11CoveredT9,T14,T16

 LINE       467
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT3,T4,T5
1CoveredT9,T14,T16

Branch Coverage for Module : tlul_adapter_sram
Line No.TotalCoveredPercent
Branches 26 24 92.31
TERNARY 108 2 2 100.00
TERNARY 293 2 2 100.00
TERNARY 299 3 2 66.67
TERNARY 344 2 2 100.00
TERNARY 467 2 2 100.00
IF 94 2 2 100.00
IF 233 4 3 75.00
IF 253 3 3 100.00
IF 314 2 2 100.00
IF 377 2 2 100.00
IF 389 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 108 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T3,T4,T5
0 Covered T3,T4,T5


LineNo. Expression -1-: 293 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Covered T9,T14,T16
0 Covered T3,T4,T5


LineNo. Expression -1-: 299 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 299 (vld_rd_rsp) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T9,T14,T16
0 0 Covered T3,T4,T5


LineNo. Expression -1-: 344 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T9,T14,T16
0 Covered T3,T4,T5


LineNo. Expression -1-: 467 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Covered T9,T14,T16
0 Covered T3,T4,T5


LineNo. Expression -1-: 94 if ((!rst_ni)) -2-: 96 if ((intg_error || rsp_fifo_error))

Branches:
-1--2-StatusTests
1 - Covered T3,T4,T5
0 1 Unreachable
0 0 Covered T3,T4,T5


LineNo. Expression -1-: 233 if (reqfifo_rvalid) -2-: 234 if (reqfifo_rdata.error) -3-: 237 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Not Covered
1 0 1 Covered T9,T14,T16
1 0 0 Covered T16,T17,T97
0 - - Covered T3,T4,T5


LineNo. Expression -1-: 253 if (reqfifo_rvalid) -2-: 254 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T9,T14,T16
1 0 Covered T16,T17,T97
0 - Covered T3,T4,T5


LineNo. Expression -1-: 314 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T3,T4,T5
0 Covered T3,T4,T5


LineNo. Expression -1-: 377 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T9,T14,T16
0 Covered T3,T4,T5


LineNo. Expression -1-: 389 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T9,T14,T16
0 Covered T3,T4,T5


Assert Coverage for Module : tlul_adapter_sram
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 13 13 100.00 13 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 13 13 100.00 13 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 539765567 539641887 0 0
DataIntgOptions_A 1355 1355 0 0
ReqOutKnown_A 539765567 539641887 0 0
SramDwHasByteGranularity_A 1355 1355 0 0
SramDwIsMultipleOfTlulWidth_A 1355 1355 0 0
TlOutKnownIfFifoKnown_A 539765567 539641887 0 0
TlOutValidKnown_A 539765567 539641887 0 0
WdataOutKnown_A 539765567 539641887 0 0
WeOutKnown_A 539765567 539641887 0 0
WmaskOutKnown_A 539765567 539641887 0 0
adapterNoReadOrWrite 1355 1355 0 0
rvalidHighReqFifoEmpty 539765567 200016 0 0
rvalidHighWhenRspFifoFull 539765567 200016 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 539765567 539641887 0 0
T3 406287 406215 0 0
T4 8913 8839 0 0
T5 4763 4663 0 0
T9 403654 403561 0 0
T10 401806 401657 0 0
T14 402704 402624 0 0
T21 402150 401991 0 0
T22 401987 401850 0 0
T23 403484 403410 0 0
T24 403886 403789 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1355 1355 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T14 1 1 0 0
T21 1 1 0 0
T22 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 539765567 539641887 0 0
T3 406287 406215 0 0
T4 8913 8839 0 0
T5 4763 4663 0 0
T9 403654 403561 0 0
T10 401806 401657 0 0
T14 402704 402624 0 0
T21 402150 401991 0 0
T22 401987 401850 0 0
T23 403484 403410 0 0
T24 403886 403789 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1355 1355 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T14 1 1 0 0
T21 1 1 0 0
T22 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1355 1355 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T14 1 1 0 0
T21 1 1 0 0
T22 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0

TlOutKnownIfFifoKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 539765567 539641887 0 0
T3 406287 406215 0 0
T4 8913 8839 0 0
T5 4763 4663 0 0
T9 403654 403561 0 0
T10 401806 401657 0 0
T14 402704 402624 0 0
T21 402150 401991 0 0
T22 401987 401850 0 0
T23 403484 403410 0 0
T24 403886 403789 0 0

TlOutValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 539765567 539641887 0 0
T3 406287 406215 0 0
T4 8913 8839 0 0
T5 4763 4663 0 0
T9 403654 403561 0 0
T10 401806 401657 0 0
T14 402704 402624 0 0
T21 402150 401991 0 0
T22 401987 401850 0 0
T23 403484 403410 0 0
T24 403886 403789 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 539765567 539641887 0 0
T3 406287 406215 0 0
T4 8913 8839 0 0
T5 4763 4663 0 0
T9 403654 403561 0 0
T10 401806 401657 0 0
T14 402704 402624 0 0
T21 402150 401991 0 0
T22 401987 401850 0 0
T23 403484 403410 0 0
T24 403886 403789 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 539765567 539641887 0 0
T3 406287 406215 0 0
T4 8913 8839 0 0
T5 4763 4663 0 0
T9 403654 403561 0 0
T10 401806 401657 0 0
T14 402704 402624 0 0
T21 402150 401991 0 0
T22 401987 401850 0 0
T23 403484 403410 0 0
T24 403886 403789 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 539765567 539641887 0 0
T3 406287 406215 0 0
T4 8913 8839 0 0
T5 4763 4663 0 0
T9 403654 403561 0 0
T10 401806 401657 0 0
T14 402704 402624 0 0
T21 402150 401991 0 0
T22 401987 401850 0 0
T23 403484 403410 0 0
T24 403886 403789 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 1355 1355 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T14 1 1 0 0
T21 1 1 0 0
T22 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 539765567 200016 0 0
T9 403654 13 0 0
T10 401806 0 0 0
T14 402704 6 0 0
T16 0 2064 0 0
T19 0 151 0 0
T20 0 170 0 0
T21 402150 0 0 0
T22 401987 0 0 0
T23 403484 0 0 0
T24 403886 0 0 0
T33 404827 0 0 0
T34 404811 0 0 0
T36 0 57 0 0
T43 403206 0 0 0
T88 0 11 0 0
T89 0 2 0 0
T90 0 16 0 0
T91 0 16 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 539765567 200016 0 0
T9 403654 13 0 0
T10 401806 0 0 0
T14 402704 6 0 0
T16 0 2064 0 0
T19 0 151 0 0
T20 0 170 0 0
T21 402150 0 0 0
T22 401987 0 0 0
T23 403484 0 0 0
T24 403886 0 0 0
T33 404827 0 0 0
T34 404811 0 0 0
T36 0 57 0 0
T43 403206 0 0 0
T88 0 11 0 0
T89 0 2 0 0
T90 0 16 0 0
T91 0 16 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%