Unified Coverage Report :: Module :: tlul_err

Module : tlul_err

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_err	67.62	76.92	68.57			25.00	100.00
tb.dut.u_reg.u_reg_if.u_err	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_err

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
67.62	76.92	68.57			25.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
67.62	76.92	68.57			25.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.37	98.55	78.63			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_reg_if.u_err

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.98	100.00	95.92			100.00	100.00	u_reg_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : tlul_err

	Line No.	Total	Covered	Percent
TOTAL		26	26	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
CONT_ASSIGN	39	1	1	100.00
CONT_ASSIGN	42	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	57	17	17	100.00
CONT_ASSIGN	96	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
32	1	1
36	1	1
39	1	1
42	1	1
54	1	1
57	1	1
58	1	1
59	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
70	1	1
72	1	1
74	1	1
78	1	1
79	1	1
80	1	1
90	1	1
91	1	1
92	1	1
96	1	1

---

Cond Coverage for Module : tlul_err

	Total	Covered	Percent
Conditions	35	35	100.00
Logical	35	35	100.00
Non-Logical	0	0
Event	0	0

 LINE       26
 EXPRESSION (tl_i.a_opcode == PutFullData)
            ---------------1--------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       27
 EXPRESSION (tl_i.a_opcode == PutPartialData)
            ----------------1----------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       28
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       39
 EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
             --------------------1--------------------   ------2-----   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T3,T4,T5
0	0	1	Covered	T63,T65,T215
0	1	0	Covered	T63,T65,T216
1	0	0	Covered	T3,T4,T5

 LINE       39
 SUB-EXPRESSION (opcode_allowed & a_config_allowed)
                 -------1------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T63,T65,T216
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       42
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
             ---------------1--------------   ----------------2----------------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T63,T65,T216
0	0	1	Covered	T3,T4,T5
0	1	0	Covered	T3,T4,T5
1	0	0	Covered	T3,T4,T5

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       72
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T4,T5,T14

 LINE       74
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T4,T5,T14

 LINE       96
 EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
             -----1-----   ----2---   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T63,T65,T215
1	0	1	Covered	T63,T65,T215
1	1	0	Covered	T63,T65,T216
1	1	1	Covered	T3,T4,T5

 LINE       96
 SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
                 ---1--   -----2----   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T3,T4,T5
0	0	1	Covered	T3,T4,T5
0	1	0	Covered	T3,T4,T5
1	0	0	Covered	T3,T4,T5

---

Branch Coverage for Module : tlul_err

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	61	8	8	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	61	if (tl_i.a_valid)
-2-:	62	case (tl_i.a_size)
-3-:	72	(tl_i.a_address[1]) ? 
-4-:	74	(tl_i.a_address[1]) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	'h0	-	-	Covered	T3,T4,T5
1	'h1	1	-	Covered	T4,T5,T14
1	'h1	0	-	Covered	T3,T4,T5
1	'h1	-	1	Covered	T4,T5,T14
1	'h1	-	0	Covered	T3,T4,T5
1	'h00000002	-	-	Covered	T3,T4,T5
1	default	-	-	Covered	T63,T65,T216
0	-	-	-	Covered	T3,T4,T5

---

Assert Coverage for Module : tlul_err

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
dataWidthOnly32_A	2885	2885	0	0

dataWidthOnly32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2885	2885	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T9	2	2	0	0
T10	2	2	0	0
T14	2	2	0	0
T21	2	2	0	0
T22	2	2	0	0
T23	2	2	0	0
T24	2	2	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_err

	Line No.	Total	Covered	Percent
TOTAL		26	20	76.92
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
CONT_ASSIGN	39	1	1	100.00
CONT_ASSIGN	42	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	57	17	11	64.71
CONT_ASSIGN	96	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
32	1	1
36	1	1
39	1	1
42	1	1
54	1	1
57	1	1
58	1	1
59	1	1
61	1	1
62	1	1
64	0	1
65	0	1
66	0	1
70	0	1
72	0	1
74	0	1
78	1	1
79	1	1
80	1	1
90	1	1
91	1	1
92	1	1
96	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_err

	Total	Covered	Percent
Conditions	35	24	68.57
Logical	35	24	68.57
Non-Logical	0	0
Event	0	0

 LINE       26
 EXPRESSION (tl_i.a_opcode == PutFullData)
            ---------------1--------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       27
 EXPRESSION (tl_i.a_opcode == PutPartialData)
            ----------------1----------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       28
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       39
 EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
             --------------------1--------------------   ------2-----   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T9,T14,T16
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Covered	T3,T4,T5

 LINE       39
 SUB-EXPRESSION (opcode_allowed & a_config_allowed)
                 -------1------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T4,T5
1	1	Covered	T9,T14,T16

 LINE       42
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
             ---------------1--------------   ----------------2----------------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Not Covered
0	0	1	Covered	T3,T4,T5
0	1	0	Covered	T3,T4,T5
1	0	0	Covered	T3,T4,T5

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       72
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       74
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       96
 EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
             -----1-----   ----2---   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T9,T14,T16

 LINE       96
 SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
                 ---1--   -----2----   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T3,T4,T5
0	0	1	Covered	T16,T17,T138
0	1	0	Covered	T3,T4,T5
1	0	0	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_err

	Line No.	Total	Covered	Percent
Branches		8	2	25.00
IF	61	8	2	25.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	61	if (tl_i.a_valid)
-2-:	62	case (tl_i.a_size)
-3-:	72	(tl_i.a_address[1]) ? 
-4-:	74	(tl_i.a_address[1]) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	'h0	-	-	Not Covered
1	'h1	1	-	Not Covered
1	'h1	0	-	Not Covered
1	'h1	-	1	Not Covered
1	'h1	-	0	Not Covered
1	'h00000002	-	-	Covered	T9,T14,T16
1	default	-	-	Not Covered
0	-	-	-	Covered	T3,T4,T5

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_err

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
dataWidthOnly32_A	1355	1355	0	0

dataWidthOnly32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1355	1355	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T14	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_reg_if.u_err

	Line No.	Total	Covered	Percent
TOTAL		26	26	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
CONT_ASSIGN	39	1	1	100.00
CONT_ASSIGN	42	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	57	17	17	100.00
CONT_ASSIGN	96	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
32	1	1
36	1	1
39	1	1
42	1	1
54	1	1
57	1	1
58	1	1
59	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
70	1	1
72	1	1
74	1	1
78	1	1
79	1	1
80	1	1
90	1	1
91	1	1
92	1	1
96	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_reg_if.u_err

	Total	Covered	Percent
Conditions	35	35	100.00
Logical	35	35	100.00
Non-Logical	0	0
Event	0	0

 LINE       26
 EXPRESSION (tl_i.a_opcode == PutFullData)
            ---------------1--------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       27
 EXPRESSION (tl_i.a_opcode == PutPartialData)
            ----------------1----------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       28
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       39
 EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
             --------------------1--------------------   ------2-----   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T3,T4,T5
0	0	1	Covered	T63,T65,T215
0	1	0	Covered	T63,T65,T216
1	0	0	Covered	T3,T5,T9

 LINE       39
 SUB-EXPRESSION (opcode_allowed & a_config_allowed)
                 -------1------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T63,T65,T216
1	0	Covered	T3,T5,T9
1	1	Covered	T3,T4,T5

 LINE       42
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
             ---------------1--------------   ----------------2----------------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T63,T65,T216
0	0	1	Covered	T3,T4,T5
0	1	0	Covered	T3,T4,T5
1	0	0	Covered	T3,T4,T5

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       72
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T4,T5,T14

 LINE       74
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T4,T5,T14

 LINE       96
 EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
             -----1-----   ----2---   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T63,T65,T215
1	0	1	Covered	T63,T65,T215
1	1	0	Covered	T63,T65,T216
1	1	1	Covered	T3,T4,T5

 LINE       96
 SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
                 ---1--   -----2----   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T3,T5,T10
0	0	1	Covered	T3,T4,T5
0	1	0	Covered	T3,T4,T5
1	0	0	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.u_reg.u_reg_if.u_err

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	61	8	8	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	61	if (tl_i.a_valid)
-2-:	62	case (tl_i.a_size)
-3-:	72	(tl_i.a_address[1]) ? 
-4-:	74	(tl_i.a_address[1]) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	'h0	-	-	Covered	T3,T4,T5
1	'h1	1	-	Covered	T4,T5,T14
1	'h1	0	-	Covered	T3,T4,T5
1	'h1	-	1	Covered	T4,T5,T14
1	'h1	-	0	Covered	T3,T4,T5
1	'h00000002	-	-	Covered	T3,T4,T5
1	default	-	-	Covered	T63,T65,T216
0	-	-	-	Covered	T3,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_reg_if.u_err

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
dataWidthOnly32_A	1530	1530	0	0

dataWidthOnly32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1530	1530	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T14	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0