USBDEV Simulation Results

Tuesday May 14 2024 19:02:33 UTC

GitHub Revision: 00fe426038

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56275124637035941820967954627144971699378360917446801543187025394370981034792

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 15.100s 8.466ms 46 50 92.00
V1 csr_hw_reset usbdev_csr_hw_reset 0.950s 194.508us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.030s 67.889us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 9.640s 1.950ms 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 3.520s 293.490us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 2.710s 99.804us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.030s 67.889us 20 20 100.00
usbdev_csr_aliasing 3.520s 293.490us 5 5 100.00
V1 mem_walk usbdev_mem_walk 4.310s 620.347us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.370s 201.799us 5 5 100.00
V1 TOTAL 111 115 96.52
V2 in_trans usbdev_in_trans 14.110s 8.461ms 49 50 98.00
V2 data_toggle_clear data_toggle_clear 0 0 --
V2 phy_pins_sense usbdev_phy_pins_sense 34.870s 18.910ms 0 50 0.00
V2 av_buffer usbdev_av_buffer 14.940s 8.379ms 50 50 100.00
V2 rx_fifo rx_fifo 0 0 --
V2 phy_config_tx_osc_test_mode phy_config_tx_osc_test_mode 0 0 --
V2 phy_config_eop_single_bit_handling usbdev_phy_config_eop_single_bit_handling 14.490s 8.376ms 48 50 96.00
V2 phy_config_pinflip phy_config_pinflip 0 0 --
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 14.640s 8.382ms 49 50 98.00
V2 max_length_out_transaction usbdev_max_length_out_transaction 15.270s 8.455ms 50 50 100.00
V2 max_length_in_transaction max_length_in_transaction 0 0 --
V2 min_length_out_transaction usbdev_min_length_out_transaction 14.090s 8.375ms 50 50 100.00
V2 min_length_in_transaction min_length_in_transaction 0 0 --
V2 random_length_out_trans usbdev_random_length_out_trans 14.500s 8.356ms 48 50 96.00
V2 random_length_in_trans random_length_in_trans 0 0 --
V2 out_stall usbdev_out_stall 32.250s 19.269ms 0 50 0.00
V2 in_stall usbdev_in_stall 14.610s 8.369ms 50 50 100.00
V2 out_iso out_iso 0 0 --
V2 in_iso usbdev_in_iso 14.090s 8.476ms 48 50 96.00
V2 pkt_received usbdev_pkt_received 15.750s 8.433ms 50 50 100.00
V2 pkt_sent usbdev_pkt_sent 13.990s 8.403ms 50 50 100.00
V2 disconnected usbdev_disconnected 14.230s 8.370ms 49 50 98.00
V2 host_lost host_lost 0 0 --
V2 link_reset link_reset 0 0 --
V2 link_suspend usbdev_link_suspend 18.520s 11.498ms 49 50 98.00
V2 link_resume link_resume 0 0 --
V2 av_empty av_empty 0 0 --
V2 rx_full rx_full 0 0 --
V2 av_overflow av_overflow 0 0 --
V2 link_in_err usbdev_link_in_err 14.240s 8.411ms 50 50 100.00
V2 rx_crc_err usbdev_rx_crc_err 14.820s 8.361ms 47 50 94.00
V2 rx_pid_err rx_pid_err 0 0 --
V2 rx_bitstuff_err usbdev_bitstuff_err 14.660s 8.350ms 22 50 44.00
V2 link_out_err link_out_err 0 0 --
V2 enable usbdev_enable 10.240s 8.365ms 0 50 0.00
V2 resume_link_active resume_link_active 0 0 --
V2 device_address device_address 0 0 --
V2 invalid_data1_data0_toggle_test invalid_data1_data0_toggle_test 0 0 --
V2 setup_stage usbdev_setup_stage 13.790s 8.386ms 50 50 100.00
V2 endpoint_access usbdev_endpoint_access 16.060s 9.221ms 46 50 92.00
V2 disable_endpoint disable_endpoint 0 0 --
V2 out_trans_nak usbdev_out_trans_nak 33.170s 18.934ms 0 50 0.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 34.450s 18.514ms 0 50 0.00
V2 nak_trans usbdev_nak_trans 14.680s 8.439ms 50 50 100.00
V2 stall_trans usbdev_stall_trans 14.110s 8.454ms 50 50 100.00
V2 setup_priority_over_stall_response setup_priority_over_stall_response 0 0 --
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 14.400s 8.393ms 50 50 100.00
V2 pending_in_trans usbdev_pending_in_trans 13.850s 8.401ms 49 50 98.00
V2 streaming_test streaming_test 0 0 --
V2 max_clock_error_untracked max_clock_error_untracked 0 0 --
V2 max_clock_error_tracking max_clock_error_tracking 0 0 --
V2 max_phase_error max_phase_error 0 0 --
V2 min_inter_pkt_delay min_inter_pkt_delay 0 0 --
V2 max_inter_pkt_delay max_inter_pkt_delay 0 0 --
V2 device_timeout_missing_host_handshake device_timeout_missing_host_handshake 0 0 --
V2 device_timeout device_timeout 0 0 --
V2 packet_buffer usbdev_pkt_buffer 1.177m 30.040ms 46 50 92.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full nak_to_out_trans_when_avbuffer_empty_rxfifo_full 0 0 --
V2 aon_wake_resume aon_wake_resume 0 0 --
V2 aon_wake_reset aon_wake_reset 0 0 --
V2 aon_wake_disconnect aon_wake_disconnect 0 0 --
V2 invalid_sync invalid_sync 0 0 --
V2 spurious_tokens_ignored spurious_tokens_ignored 0 0 --
V2 low_speed_traffic low_speed_traffic 0 0 --
V2 rand_bus_resets rand_bus_resets 0 0 --
V2 rand_disconnects rand_disconnects 0 0 --
V2 max_usb_traffic max_usb_traffic 0 0 --
V2 stress_usb_traffic stress_usb_traffic 0 0 --
V2 in_packet_retraction in_packet_retraction 0 0 --
V2 data_toggle_restore usbdev_data_toggle_restore 14.860s 8.377ms 0 50 0.00
V2 setup_priority setup_priority 0 0 --
V2 fifo_resets usbdev_fifo_rst 17.440s 8.482ms 50 50 100.00
V2 intr_test usbdev_intr_test 0.770s 60.221us 50 50 100.00
V2 alert_test usbdev_alert_test 0 0 --
V2 tl_d_oob_addr_access usbdev_tl_errors 3.360s 117.436us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.360s 117.436us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 0.950s 194.508us 5 5 100.00
usbdev_csr_rw 1.030s 67.889us 20 20 100.00
usbdev_csr_aliasing 3.520s 293.490us 5 5 100.00
usbdev_same_csr_outstanding 1.810s 194.922us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 0.950s 194.508us 5 5 100.00
usbdev_csr_rw 1.030s 67.889us 20 20 100.00
usbdev_csr_aliasing 3.520s 293.490us 5 5 100.00
usbdev_same_csr_outstanding 1.810s 194.922us 20 20 100.00
V2 TOTAL 1240 1590 77.99
V2S tl_intg_err usbdev_sec_cm 3.170s 2.458ms 5 5 100.00
usbdev_tl_intg_err 5.330s 740.757us 20 20 100.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 5.330s 740.757us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
Unmapped tests usbdev_dpi_config_host 2.332m 5.107ms 1 1 100.00
usbdev_out_iso 15.100s 8.440ms 49 50 98.00
random_length_in_trans 14.310s 8.470ms 47 50 94.00
min_length_in_transaction 14.740s 8.397ms 50 50 100.00
max_length_in_transaction 15.620s 8.464ms 49 50 98.00
usbdev_stress_all_with_rand_reset 0.700s 96.900us 0 50 0.00
usbdev_stress_all 0.610s 0 50 0.00
TOTAL 1426 1881 75.81

Testplan Progress

Items Total Written Passing Progress
N.A. 4 4 1 25.00
V1 8 8 7 87.50
V2 76 33 15 19.74
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
90.48 96.96 90.29 97.43 59.38 94.95 97.96 96.40

Failure Buckets

Past Results