Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5214176	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	513293	1		T2	23		T3	5		T4	6163

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	5453796	1		T2	3098		T3	2964		T4	6683
values[0x0]	136505	1		T2	3		T3	3		T4	1482
values[0x1]	137168	1		T2	3		T3	5		T4	1428

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3915159	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	1812310	1		T2	818		T3	766		T4	6995

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26192	1		T3	15		T4	39		T17	7
valid_sources[0x01]	25870	1		T3	11		T4	39		T17	13
valid_sources[0x02]	20701	1		T3	7		T4	34		T17	9
valid_sources[0x03]	26962	1		T3	20		T4	34		T17	7
valid_sources[0x04]	20359	1		T3	8		T4	33		T17	8
valid_sources[0x05]	17348	1		T3	10		T4	32		T17	13
valid_sources[0x06]	21003	1		T3	9		T4	33		T17	13
valid_sources[0x07]	17668	1		T3	5		T4	37		T17	17
valid_sources[0x08]	23721	1		T3	7		T4	36		T17	9
valid_sources[0x09]	25956	1		T3	18		T4	36		T17	10
valid_sources[0x0a]	23079	1		T3	11		T4	48		T17	18
valid_sources[0x0b]	17300	1		T3	19		T4	40		T17	20
valid_sources[0x0c]	23895	1		T3	19		T4	35		T17	14
valid_sources[0x0d]	16905	1		T3	10		T4	40		T17	15
valid_sources[0x0e]	17849	1		T3	14		T4	43		T17	11
valid_sources[0x0f]	17447	1		T3	14		T4	32		T17	6
valid_sources[0x10]	20369	1		T3	11		T4	32		T17	9
valid_sources[0x11]	28581	1		T3	7		T4	41		T17	4
valid_sources[0x12]	16879	1		T3	13		T4	48		T17	15
valid_sources[0x13]	25847	1		T3	14		T4	44		T17	12
valid_sources[0x14]	22060	1		T3	11		T4	34		T17	11
valid_sources[0x15]	23313	1		T3	9		T4	35		T17	19
valid_sources[0x16]	19920	1		T3	13		T4	30		T17	8
valid_sources[0x17]	22769	1		T3	9		T4	43		T17	14
valid_sources[0x18]	21511	1		T3	10		T4	28		T17	9
valid_sources[0x19]	20012	1		T3	11		T4	33		T17	14
valid_sources[0x1a]	26163	1		T3	10		T4	39		T17	18
valid_sources[0x1b]	20018	1		T3	8		T4	42		T17	11
valid_sources[0x1c]	17311	1		T3	11		T4	44		T17	16
valid_sources[0x1d]	20254	1		T3	5		T4	33		T17	6
valid_sources[0x1e]	22622	1		T3	11		T4	42		T17	18
valid_sources[0x1f]	19717	1		T3	8		T4	32		T17	7
valid_sources[0x20]	21726	1		T3	9		T4	40		T17	8
valid_sources[0x21]	16769	1		T3	10		T4	27		T17	8
valid_sources[0x22]	17930	1		T3	11		T4	42		T17	16
valid_sources[0x23]	26328	1		T3	12		T4	50		T17	9
valid_sources[0x24]	22857	1		T3	12		T4	43		T17	7
valid_sources[0x25]	25932	1		T3	17		T4	43		T17	13
valid_sources[0x26]	19582	1		T3	12		T4	33		T17	17
valid_sources[0x27]	20235	1		T3	20		T4	35		T17	25
valid_sources[0x28]	25188	1		T3	8		T4	33		T17	23
valid_sources[0x29]	22720	1		T3	13		T4	29		T17	8
valid_sources[0x2a]	16788	1		T3	6		T4	38		T17	13
valid_sources[0x2b]	22767	1		T3	12		T4	40		T17	16
valid_sources[0x2c]	19201	1		T3	18		T4	51		T17	10
valid_sources[0x2d]	29147	1		T3	16		T4	39		T17	7
valid_sources[0x2e]	22332	1		T3	18		T4	35		T17	12
valid_sources[0x2f]	17295	1		T3	13		T4	41		T17	13
valid_sources[0x30]	17376	1		T3	11		T4	44		T17	11
valid_sources[0x31]	20258	1		T3	15		T4	36		T17	1
valid_sources[0x32]	30347	1		T3	18		T4	35		T17	7
valid_sources[0x33]	23628	1		T3	3		T4	35		T17	5
valid_sources[0x34]	23577	1		T3	12		T4	35		T17	11
valid_sources[0x35]	23316	1		T3	12		T4	40		T17	4
valid_sources[0x36]	23203	1		T3	14		T4	28		T17	16
valid_sources[0x37]	26037	1		T3	4		T4	32		T17	10
valid_sources[0x38]	23780	1		T3	14		T4	38		T17	11
valid_sources[0x39]	20815	1		T3	5		T4	40		T17	16
valid_sources[0x3a]	26933	1		T3	7		T4	38		T17	10
valid_sources[0x3b]	35417	1		T3	17		T4	26		T17	10
valid_sources[0x3c]	20313	1		T3	14		T4	46		T17	11
valid_sources[0x3d]	17439	1		T3	11		T4	37		T17	6
valid_sources[0x3e]	26624	1		T3	10		T4	31		T17	10
valid_sources[0x3f]	17619	1		T3	9		T4	53		T17	9
valid_sources[0x40]	23783	1		T3	6		T4	43		T17	14
valid_sources[0x41]	24607	1		T3	10		T4	41		T17	9
valid_sources[0x42]	23243	1		T3	10		T4	45		T17	6
valid_sources[0x43]	20599	1		T3	5		T4	31		T17	5
valid_sources[0x44]	18248	1		T3	8		T4	25		T17	5
valid_sources[0x45]	20432	1		T3	17		T4	27		T17	17
valid_sources[0x46]	20623	1		T3	8		T4	27		T17	12
valid_sources[0x47]	17604	1		T3	9		T4	41		T17	9
valid_sources[0x48]	23521	1		T3	13		T4	37		T17	11
valid_sources[0x49]	29751	1		T3	5		T4	35		T17	17
valid_sources[0x4a]	22855	1		T3	17		T4	53		T17	7
valid_sources[0x4b]	20829	1		T3	18		T4	35		T17	13
valid_sources[0x4c]	21592	1		T3	19		T4	42		T17	18
valid_sources[0x4d]	20118	1		T3	16		T4	31		T17	6
valid_sources[0x4e]	20984	1		T3	13		T4	44		T17	20
valid_sources[0x4f]	23054	1		T3	9		T4	36		T17	8
valid_sources[0x50]	25677	1		T3	11		T4	45		T17	7
valid_sources[0x51]	17445	1		T3	11		T4	28		T17	20
valid_sources[0x52]	17242	1		T3	10		T4	31		T17	15
valid_sources[0x53]	28957	1		T3	8		T4	40		T17	8
valid_sources[0x54]	26128	1		T3	8		T4	34		T17	7
valid_sources[0x55]	24221	1		T3	10		T4	38		T17	17
valid_sources[0x56]	20353	1		T3	14		T4	36		T17	14
valid_sources[0x57]	22967	1		T3	13		T4	39		T17	9
valid_sources[0x58]	21004	1		T3	6		T4	44		T17	8
valid_sources[0x59]	19971	1		T3	12		T4	41		T17	12
valid_sources[0x5a]	17525	1		T3	11		T4	34		T17	12
valid_sources[0x5b]	20386	1		T3	5		T4	50		T17	10
valid_sources[0x5c]	24954	1		T3	13		T4	43		T17	10
valid_sources[0x5d]	24361	1		T3	14		T4	41		T17	5
valid_sources[0x5e]	32202	1		T3	16		T4	34		T17	16
valid_sources[0x5f]	23494	1		T3	11		T4	31		T17	29
valid_sources[0x60]	19690	1		T3	12		T4	43		T17	5
valid_sources[0x61]	24132	1		T3	11		T4	37		T17	8
valid_sources[0x62]	16923	1		T3	11		T4	28		T17	10
valid_sources[0x63]	20226	1		T3	12		T4	34		T17	10
valid_sources[0x64]	23743	1		T3	9		T4	46		T17	12
valid_sources[0x65]	29034	1		T3	14		T4	37		T17	10
valid_sources[0x66]	22813	1		T3	14		T4	33		T17	9
valid_sources[0x67]	29563	1		T3	8		T4	41		T17	12
valid_sources[0x68]	23472	1		T3	13		T4	55		T17	10
valid_sources[0x69]	26264	1		T3	9		T4	50		T17	17
valid_sources[0x6a]	17417	1		T3	10		T4	41		T17	15
valid_sources[0x6b]	23249	1		T3	10		T4	40		T17	21
valid_sources[0x6c]	25938	1		T3	19		T4	37		T17	21
valid_sources[0x6d]	29664	1		T3	13		T4	36		T17	11
valid_sources[0x6e]	23080	1		T2	3104		T3	13		T4	40
valid_sources[0x6f]	26437	1		T3	14		T4	46		T17	5
valid_sources[0x70]	20366	1		T3	9		T4	41		T17	14
valid_sources[0x71]	24562	1		T3	13		T4	30		T17	9
valid_sources[0x72]	16687	1		T3	11		T4	44		T17	16
valid_sources[0x73]	17365	1		T3	10		T4	39		T17	13
valid_sources[0x74]	18228	1		T3	18		T4	42		T17	11
valid_sources[0x75]	20295	1		T3	10		T4	36		T17	10
valid_sources[0x76]	23437	1		T3	14		T4	43		T17	13
valid_sources[0x77]	19678	1		T3	16		T4	49		T17	7
valid_sources[0x78]	24722	1		T3	9		T4	48		T17	6
valid_sources[0x79]	17468	1		T3	6		T4	35		T17	12
valid_sources[0x7a]	22840	1		T3	10		T4	42		T17	17
valid_sources[0x7b]	16859	1		T3	13		T4	34		T17	24
valid_sources[0x7c]	20236	1		T3	10		T4	42		T17	13
valid_sources[0x7d]	22946	1		T3	16		T4	39		T17	12
valid_sources[0x7e]	28835	1		T3	15		T4	47		T17	13
valid_sources[0x7f]	21783	1		T3	6		T4	31		T17	10
valid_sources[0x80]	25969	1		T3	9		T4	35		T17	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

292753

1

T2

20

T3

1

T4

3465

values[0x0]

all_enables

biggest_size

114628

1

T2

3

T3

2

T4

1386

values[0x1]

all_enables

biggest_size

105912

1

T3

2

T4

1312

T5

5