Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	5229737	1		T2	3081		T3	2967		T4	3430
full_word	514445	1		T2	23		T3	5		T4	6163

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	5743892	1		T2	3104		T3	2972		T4	9593
auto[TlIntgErrCmd]	114	1		T236	5		T237	6		T233	12
auto[TlIntgErrData]	91	1		T236	3		T237	8		T233	2
auto[TlIntgErrBoth]	85	1		T236	2		T237	6		T233	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5455822	1		T2	3098		T3	2964		T4	6683
auto[1]	288360	1		T2	6		T3	8		T4	2910

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5162742	1		T2	3078		T3	2963		T4	3218
auto[TlIntgErrNone]	partial	auto[1]	66727	1		T2	3		T3	4		T4	212
auto[TlIntgErrNone]	full_word	auto[0]	292952	1		T2	20		T3	1		T4	3465
auto[TlIntgErrNone]	full_word	auto[1]	221471	1		T2	3		T3	4		T4	2698
auto[TlIntgErrCmd]	partial	auto[0]	49	1		T236	3		T237	3		T233	7
auto[TlIntgErrCmd]	partial	auto[1]	57	1		T236	1		T237	2		T233	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T237	1		T233	1		T295	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T236	1		T297	1		T294	2
auto[TlIntgErrData]	partial	auto[0]	37	1		T236	2		T237	2		T295	2
auto[TlIntgErrData]	partial	auto[1]	47	1		T237	5		T233	1		T295	1
auto[TlIntgErrData]	full_word	auto[0]	4	1		T236	1		T298	1		T277	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T237	1		T233	1		T277	1
auto[TlIntgErrBoth]	partial	auto[0]	32	1		T237	4		T233	1		T276	5
auto[TlIntgErrBoth]	partial	auto[1]	46	1		T236	2		T237	1		T233	5
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T277	1		T299	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T237	1		T297	1		T300	1