Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.84	93.83	70.15	93.58		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	726042815	12784	0	0
ep_in_enable_rd_A	726042815	3874	0	0
ep_out_enable_rd_A	726042815	4042	0	0
in_iso_rd_A	726042815	4212	0	0
intr_enable_rd_A	726042815	6033	0	0
out_iso_rd_A	726042815	4106	0	0
phy_config_rd_A	726042815	2959	0	0
phy_pins_drive_rd_A	726042815	3444	0	0
rxenable_setup_rd_A	726042815	3518	0	0
set_nak_out_rd_A	726042815	4076	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726042815	12784	0	0
T65	10304	864	0	0
T66	15833	765	0	0
T67	4466	16	0	0
T70	3737	6	0	0
T73	4016	11	0	0
T116	2729	12	0	0
T232	5272	284	0	0
T243	8628	632	0	0
T246	7084	390	0	0
T249	4686	6	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726042815	3874	0	0
T1	6916	11	0	0
T72	4368	2	0	0
T117	17218	36	0	0
T237	35594	129	0	0
T249	4686	14	0	0
T256	3585	1	0	0
T276	30931	485	0	0
T277	59879	506	0	0
T278	10267	111	0	0
T279	5502	24	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726042815	4042	0	0
T1	6916	7	0	0
T72	4368	9	0	0
T117	17218	23	0	0
T237	35594	263	0	0
T249	4686	10	0	0
T256	3585	2	0	0
T276	30931	511	0	0
T277	59879	505	0	0
T278	10267	112	0	0
T279	5502	13	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726042815	4212	0	0
T1	6916	8	0	0
T72	4368	77	0	0
T117	17218	61	0	0
T237	35594	284	0	0
T249	4686	5	0	0
T256	3585	4	0	0
T276	30931	341	0	0
T277	59879	405	0	0
T278	10267	91	0	0
T279	5502	29	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726042815	6033	0	0
T1	6916	8	0	0
T72	4368	79	0	0
T82	1668	7	0	0
T83	2380	22	0	0
T117	17218	50	0	0
T237	35594	282	0	0
T249	4686	50	0	0
T280	1589	8	0	0
T281	1622	16	0	0
T282	1479	9	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726042815	4106	0	0
T1	6916	7	0	0
T72	4368	56	0	0
T117	17218	65	0	0
T237	35594	381	0	0
T249	4686	14	0	0
T256	3585	13	0	0
T276	30931	386	0	0
T277	59879	460	0	0
T278	10267	98	0	0
T279	5502	27	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726042815	2959	0	0
T1	6916	5	0	0
T72	4368	14	0	0
T117	17218	25	0	0
T237	35594	221	0	0
T247	16549	1	0	0
T249	4686	44	0	0
T256	3585	4	0	0
T276	30931	275	0	0
T277	59879	301	0	0
T278	10267	88	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726042815	3444	0	0
T1	6916	5	0	0
T72	4368	32	0	0
T117	17218	32	0	0
T237	35594	156	0	0
T249	4686	50	0	0
T256	3585	2	0	0
T276	30931	308	0	0
T277	59879	402	0	0
T278	10267	117	0	0
T279	5502	8	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726042815	3518	0	0
T1	6916	4	0	0
T72	4368	40	0	0
T117	17218	25	0	0
T237	35594	206	0	0
T249	4686	51	0	0
T256	3585	11	0	0
T276	30931	310	0	0
T277	59879	441	0	0
T278	10267	112	0	0
T279	5502	37	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726042815	4076	0	0
T1	6916	3	0	0
T72	4368	80	0	0
T117	17218	24	0	0
T237	35594	321	0	0
T249	4686	9	0	0
T256	3585	9	0	0
T276	30931	468	0	0
T277	59879	659	0	0
T278	10267	101	0	0
T283	4731	5	0	0