Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.91	100.00	67.63			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_rxfifo	90.62	100.00	62.50			100.00	100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo	90.62	100.00	62.50			100.00	100.00
tb.dut.usbdev_avsetupfifo	91.07	100.00	64.29			100.00	100.00
tb.dut.usbdev_avoutfifo	91.07	100.00	64.29			100.00	100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo	92.19	100.00	68.75			100.00	100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo	93.75	100.00	75.00			100.00	100.00
tb.dut.u_reg.u_socket.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.usbdev_rxfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.62	100.00	62.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.47	95.12	77.78			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.84	93.83	70.15	93.58		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	86.51	92.59	90.00			76.92

---

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.62	100.00	62.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.64	95.00	72.22			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.37	98.55	78.63			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

---

Module Instance : tb.dut.usbdev_avsetupfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.07	100.00	64.29			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	100.00	85.29			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.84	93.83	70.15	93.58		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.usbdev_avoutfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.07	100.00	64.29			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	100.00	85.29			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.84	93.83	70.15	93.58		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.37	98.55	78.63			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

---

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.32	95.00	77.27			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.37	98.55	78.63			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

---

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=0,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
91.07	100.00

tb.dut.usbdev_avsetupfifo

SCORE	LINE
91.07	100.00

tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.62	100.00

tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.fifo_h.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.fifo_h.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
92.19	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

SCORE	LINE
90.62	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.75	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.75	75.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T17,T109,T110
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T2,T4,T17

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T17

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T17,T19
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T17

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T4,T17

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T4,T17

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T109,T110
1	0	Covered	T2,T4,T17
1	1	Covered	T2,T3,T4

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T4,T17
1	Covered	T2,T3,T4

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=0,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
91.07	64.29

tb.dut.usbdev_avsetupfifo

SCORE	COND
91.07	64.29

tb.dut.usbdev_avoutfifo

	Total	Covered	Percent
Conditions	14	9	64.29
Logical	14	9	64.29
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T57,T58,T59
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T5

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 + Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
90.62	62.50

tb.dut.usbdev_rxfifo

SCORE	COND
92.19	68.75

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T17
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T2,T4,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T5

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T2,T3,T4

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
90.62	62.50

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T17
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T2,T4,T17

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T17

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T17

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T4,T17
1	Covered	T2,T3,T4

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=0,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
91.07	100.00

tb.dut.usbdev_avsetupfifo

SCORE	BRANCH
91.07	100.00

tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T2,T3,T4

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
93.75	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T17
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T2,T4,T17

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T17
0	Covered	T2,T3,T4

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 + Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
90.62	100.00

tb.dut.usbdev_rxfifo

SCORE	BRANCH
92.19	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

SCORE	BRANCH
90.62	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T2,T3,T4

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	61745756	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	2147483647	28549511	0	0
gen_passthru_fifo.paramCheckPass	11208	11208	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	61745756	0	0
T2	4442240	14836	0	0
T3	4431526	14084	0	0
T4	10522050	427933	0	0
T5	6095672	14261	0	0
T17	4552746	37445	0	0
T18	4491025	13968	0	0
T19	4865604	15017	0	0
T20	4844652	14857	0	0
T21	4822320	13535	0	0
T22	4873344	14860	0	0
T23	402374	0	0	0
T24	406308	0	0	0
T25	403332	0	0	0
T28	402782	0	0	0
T34	401758	0	0	0
T37	0	557	0	0
T38	0	1180	0	0
T48	0	956	0	0
T57	0	4755	0	0
T58	0	1619	0	0
T60	0	1497	0	0
T75	0	20	0	0
T76	0	45	0	0
T109	0	94	0	0
T111	404435	80	0	0
T112	0	25	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T2	4846080	4845204	0	0
T3	4834392	4833456	0	0
T4	11478600	11477904	0	0
T5	6649824	6649104	0	0
T17	4966632	4966020	0	0
T18	4899300	4898604	0	0
T19	4865604	4864980	0	0
T20	4844652	4843536	0	0
T21	4822320	4821156	0	0
T22	4873344	4872696	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T2	4846080	4845204	0	0
T3	4834392	4833456	0	0
T4	11478600	11477904	0	0
T5	6649824	6649104	0	0
T17	4966632	4966020	0	0
T18	4899300	4898604	0	0
T19	4865604	4864980	0	0
T20	4844652	4843536	0	0
T21	4822320	4821156	0	0
T22	4873344	4872696	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T2	4846080	4845204	0	0
T3	4834392	4833456	0	0
T4	11478600	11477904	0	0
T5	6649824	6649104	0	0
T17	4966632	4966020	0	0
T18	4899300	4898604	0	0
T19	4865604	4864980	0	0
T20	4844652	4843536	0	0
T21	4822320	4821156	0	0
T22	4873344	4872696	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	28549511	0	0
T2	2019200	2420	0	0
T3	2014330	2196	0	0
T4	4782750	388512	0	0
T5	2770760	1885	0	0
T17	2069430	5703	0	0
T18	2041375	2072	0	0
T19	2432802	2529	0	0
T20	2422326	2965	0	0
T21	2411160	1183	0	0
T22	2436672	2436	0	0
T23	402374	0	0	0
T24	406308	0	0	0
T25	403332	0	0	0
T28	402782	0	0	0
T34	401758	0	0	0
T37	0	557	0	0
T38	0	1180	0	0
T48	0	956	0	0
T57	0	4755	0	0
T58	0	1619	0	0
T60	0	1497	0	0
T75	0	12	0	0
T76	0	27	0	0
T109	0	60	0	0
T111	404435	48	0	0
T112	0	15	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	11208	11208	0	0
T2	6	6	0	0
T3	6	6	0	0
T4	6	6	0	0
T5	6	6	0	0
T17	6	6	0	0
T18	6	6	0	0
T19	6	6	0	0
T20	6	6	0	0
T21	6	6	0	0
T22	6	6	0	0

Line Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T2,T4,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T5

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	724486299	2347758	0	0
DepthKnown_A	724486299	724355018	0	0
RvalidKnown_A	724486299	724355018	0	0
WreadyKnown_A	724486299	724355018	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	724486299	2347758	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724486299	2347758	0	0
T2	403840	100	0	0
T3	402866	0	0	0
T4	956550	27925	0	0
T5	554152	98	0	0
T17	413886	419	0	0
T18	408275	3133	0	0
T19	405467	196	0	0
T20	403721	0	0	0
T21	401860	0	0	0
T22	406112	4	0	0
T23	0	1283	0	0
T24	0	3197	0	0
T25	0	1523	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724486299	724355018	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724486299	724355018	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724486299	724355018	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	724486299	2347758	0	0
T2	403840	100	0	0
T3	402866	0	0	0
T4	956550	27925	0	0
T5	554152	98	0	0
T17	413886	419	0	0
T18	408275	3133	0	0
T19	405467	196	0	0
T20	403721	0	0	0
T21	401860	0	0	0
T22	406112	4	0	0
T23	0	1283	0	0
T24	0	3197	0	0
T25	0	1523	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T17
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T2,T4,T17

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T17

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T17

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T4,T17
1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T2,T4,T17

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T17
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	724486299	198099	0	0
DepthKnown_A	724486299	724355018	0	0
RvalidKnown_A	724486299	724355018	0	0
WreadyKnown_A	724486299	724355018	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	724486299	198099	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724486299	198099	0	0
T2	403840	16	0	0
T3	402866	0	0	0
T4	956550	3318	0	0
T5	554152	0	0	0
T17	413886	34	0	0
T18	408275	0	0	0
T19	405467	15	0	0
T20	403721	0	0	0
T21	401860	0	0	0
T22	406112	16	0	0
T75	0	4	0	0
T76	0	9	0	0
T109	0	8	0	0
T111	0	16	0	0
T112	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724486299	724355018	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724486299	724355018	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724486299	724355018	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	724486299	198099	0	0
T2	403840	16	0	0
T3	402866	0	0	0
T4	956550	3318	0	0
T5	554152	0	0	0
T17	413886	34	0	0
T18	408275	0	0	0
T19	405467	15	0	0
T20	403721	0	0	0
T21	401860	0	0	0
T22	406112	16	0	0
T75	0	4	0	0
T76	0	9	0	0
T109	0	8	0	0
T111	0	16	0	0
T112	0	5	0	0

Line Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Covered	Percent
Conditions	14	9	64.29
Logical	14	9	64.29
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T57,T58,T59
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T19,T37,T57

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T19,T37,T57

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T19,T37,T57
1	1	0	Not Covered
1	1	1	Covered	T19,T37,T38

---

Branch Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T19,T37,T57
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	724486299	580642	0	0
DepthKnown_A	724486299	724355018	0	0
RvalidKnown_A	724486299	724355018	0	0
WreadyKnown_A	724486299	724355018	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	724486299	580642	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724486299	580642	0	0
T19	405467	552	0	0
T20	403721	0	0	0
T21	401860	0	0	0
T22	406112	0	0	0
T23	402374	0	0	0
T24	406308	0	0	0
T25	403332	0	0	0
T28	402782	0	0	0
T34	401758	0	0	0
T37	0	557	0	0
T38	0	1180	0	0
T46	0	560	0	0
T48	0	956	0	0
T57	0	4755	0	0
T58	0	1619	0	0
T59	0	6054	0	0
T60	0	1497	0	0
T111	404435	0	0	0
T113	0	2345	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724486299	724355018	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724486299	724355018	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724486299	724355018	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	724486299	580642	0	0
T19	405467	552	0	0
T20	403721	0	0	0
T21	401860	0	0	0
T22	406112	0	0	0
T23	402374	0	0	0
T24	406308	0	0	0
T25	403332	0	0	0
T28	402782	0	0	0
T34	401758	0	0	0
T37	0	557	0	0
T38	0	1180	0	0
T46	0	560	0	0
T48	0	956	0	0
T57	0	4755	0	0
T58	0	1619	0	0
T59	0	6054	0	0
T60	0	1497	0	0
T111	404435	0	0	0
T113	0	2345	0	0

Line Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Covered	Percent
Conditions	14	9	64.29
Logical	14	9	64.29
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T57,T58,T59
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T5

---

Branch Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	724486299	24428122	0	0
DepthKnown_A	724486299	724355018	0	0
RvalidKnown_A	724486299	724355018	0	0
WreadyKnown_A	724486299	724355018	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	724486299	24428122	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724486299	24428122	0	0
T2	403840	2372	0	0
T3	402866	2196	0	0
T4	956550	376421	0	0
T5	554152	1885	0	0
T17	413886	5355	0	0
T18	408275	2072	0	0
T19	405467	1924	0	0
T20	403721	2965	0	0
T21	401860	1183	0	0
T22	406112	2388	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724486299	724355018	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724486299	724355018	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724486299	724355018	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	724486299	24428122	0	0
T2	403840	2372	0	0
T3	402866	2196	0	0
T4	956550	376421	0	0
T5	554152	1885	0	0
T17	413886	5355	0	0
T18	408275	2072	0	0
T19	405467	1924	0	0
T20	403721	2965	0	0
T21	401860	1183	0	0
T22	406112	2388	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T17
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T2,T4,T17

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T17

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T17,T19
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T17

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T4,T17
1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T2,T4,T17

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T17
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	724486299	619980	0	0
DepthKnown_A	724486299	724355018	0	0
RvalidKnown_A	724486299	724355018	0	0
WreadyKnown_A	724486299	724355018	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	724486299	619980	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724486299	619980	0	0
T2	403840	16	0	0
T3	402866	0	0	0
T4	956550	5455	0	0
T5	554152	0	0	0
T17	413886	157	0	0
T18	408275	0	0	0
T19	405467	23	0	0
T20	403721	0	0	0
T21	401860	0	0	0
T22	406112	16	0	0
T75	0	4	0	0
T76	0	9	0	0
T109	0	26	0	0
T111	0	16	0	0
T112	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724486299	724355018	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724486299	724355018	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724486299	724355018	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	724486299	619980	0	0
T2	403840	16	0	0
T3	402866	0	0	0
T4	956550	5455	0	0
T5	554152	0	0	0
T17	413886	157	0	0
T18	408275	0	0	0
T19	405467	23	0	0
T20	403721	0	0	0
T21	401860	0	0	0
T22	406112	16	0	0
T75	0	4	0	0
T76	0	9	0	0
T109	0	26	0	0
T111	0	16	0	0
T112	0	5	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T17,T109,T110
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T2,T4,T17

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T17

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T17,T19
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T17

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T4,T17

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T4,T17

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T109,T110
1	0	Covered	T2,T4,T17
1	1	Covered	T2,T3,T4

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T4,T17
1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T17
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T2,T4,T17

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T17
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	724486299	374910	0	0
DepthKnown_A	724486299	724355018	0	0
RvalidKnown_A	724486299	724355018	0	0
WreadyKnown_A	724486299	724355018	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	724486299	374910	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724486299	374910	0	0
T2	403840	16	0	0
T3	402866	0	0	0
T4	956550	3318	0	0
T5	554152	0	0	0
T17	413886	157	0	0
T18	408275	0	0	0
T19	405467	15	0	0
T20	403721	0	0	0
T21	401860	0	0	0
T22	406112	16	0	0
T75	0	4	0	0
T76	0	9	0	0
T109	0	26	0	0
T111	0	16	0	0
T112	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724486299	724355018	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724486299	724355018	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724486299	724355018	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	724486299	374910	0	0
T2	403840	16	0	0
T3	402866	0	0	0
T4	956550	3318	0	0
T5	554152	0	0	0
T17	413886	157	0	0
T18	408275	0	0	0
T19	405467	15	0	0
T20	403721	0	0	0
T21	401860	0	0	0
T22	406112	16	0	0
T75	0	4	0	0
T76	0	9	0	0
T109	0	26	0	0
T111	0	16	0	0
T112	0	5	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	726042815	5952255	0	0
DepthKnown_A	726042815	725864092	0	0
RvalidKnown_A	726042815	725864092	0	0
WreadyKnown_A	726042815	725864092	0	0
gen_passthru_fifo.paramCheckPass	1868	1868	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726042815	5952255	0	0
T2	403840	3104	0	0
T3	402866	2972	0	0
T4	956550	10642	0	0
T5	554152	3094	0	0
T17	413886	2997	0	0
T18	408275	2974	0	0
T19	405467	3122	0	0
T20	403721	2973	0	0
T21	401860	3088	0	0
T22	406112	3106	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726042815	725864092	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726042815	725864092	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726042815	725864092	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1868	1868	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	726042815	10674222	0	0
DepthKnown_A	726042815	725864092	0	0
RvalidKnown_A	726042815	725864092	0	0
WreadyKnown_A	726042815	725864092	0	0
gen_passthru_fifo.paramCheckPass	1868	1868	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726042815	10674222	0	0
T2	403840	3104	0	0
T3	402866	2972	0	0
T4	956550	9593	0	0
T5	554152	3094	0	0
T17	413886	12874	0	0
T18	408275	2974	0	0
T19	405467	3122	0	0
T20	403721	2973	0	0
T21	401860	3088	0	0
T22	406112	3106	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726042815	725864092	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726042815	725864092	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726042815	725864092	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1868	1868	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	726042815	365928	0	0
DepthKnown_A	726042815	725864092	0	0
RvalidKnown_A	726042815	725864092	0	0
WreadyKnown_A	726042815	725864092	0	0
gen_passthru_fifo.paramCheckPass	1868	1868	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726042815	365928	0	0
T2	403840	16	0	0
T3	402866	0	0	0
T4	956550	5455	0	0
T5	554152	0	0	0
T17	413886	34	0	0
T18	408275	0	0	0
T19	405467	23	0	0
T20	403721	0	0	0
T21	401860	0	0	0
T22	406112	16	0	0
T75	0	4	0	0
T76	0	9	0	0
T109	0	8	0	0
T111	0	16	0	0
T112	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726042815	725864092	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726042815	725864092	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726042815	725864092	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1868	1868	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	726042815	677959	0	0
DepthKnown_A	726042815	725864092	0	0
RvalidKnown_A	726042815	725864092	0	0
WreadyKnown_A	726042815	725864092	0	0
gen_passthru_fifo.paramCheckPass	1868	1868	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726042815	677959	0	0
T2	403840	16	0	0
T3	402866	0	0	0
T4	956550	5455	0	0
T5	554152	0	0	0
T17	413886	157	0	0
T18	408275	0	0	0
T19	405467	23	0	0
T20	403721	0	0	0
T21	401860	0	0	0
T22	406112	16	0	0
T75	0	4	0	0
T76	0	9	0	0
T109	0	26	0	0
T111	0	16	0	0
T112	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726042815	725864092	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726042815	725864092	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726042815	725864092	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1868	1868	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	726042815	5529618	0	0
DepthKnown_A	726042815	725864092	0	0
RvalidKnown_A	726042815	725864092	0	0
WreadyKnown_A	726042815	725864092	0	0
gen_passthru_fifo.paramCheckPass	1868	1868	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726042815	5529618	0	0
T2	403840	3088	0	0
T3	402866	2972	0	0
T4	956550	4138	0	0
T5	554152	3094	0	0
T17	413886	2963	0	0
T18	408275	2974	0	0
T19	405467	3099	0	0
T20	403721	2973	0	0
T21	401860	3088	0	0
T22	406112	3090	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726042815	725864092	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726042815	725864092	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726042815	725864092	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1868	1868	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	726042815	9996263	0	0
DepthKnown_A	726042815	725864092	0	0
RvalidKnown_A	726042815	725864092	0	0
WreadyKnown_A	726042815	725864092	0	0
gen_passthru_fifo.paramCheckPass	1868	1868	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726042815	9996263	0	0
T2	403840	3088	0	0
T3	402866	2972	0	0
T4	956550	4138	0	0
T5	554152	3094	0	0
T17	413886	12717	0	0
T18	408275	2974	0	0
T19	405467	3099	0	0
T20	403721	2973	0	0
T21	401860	3088	0	0
T22	406112	3090	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726042815	725864092	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726042815	725864092	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726042815	725864092	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1868	1868	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0