Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.56	97.53	79.85	95.41		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	973283728	13499	0	0
ep_in_enable_rd_A	973283728	2449	0	0
ep_out_enable_rd_A	973283728	2658	0	0
in_iso_rd_A	973283728	2605	0	0
intr_enable_rd_A	973283728	3712	0	0
out_iso_rd_A	973283728	2358	0	0
phy_config_rd_A	973283728	1629	0	0
phy_pins_drive_rd_A	973283728	2193	0	0
rxenable_setup_rd_A	973283728	2826	0	0
set_nak_out_rd_A	973283728	2357	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	973283728	13499	0	0
T207	10133	23	0	0
T208	5280	279	0	0
T209	8586	587	0	0
T231	42441	4	0	0
T232	25755	2	0	0
T234	12106	20	0	0
T235	38474	3	0	0
T237	4810	613	0	0
T238	5487	669	0	0
T242	23722	4	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	973283728	2449	0	0
T207	10133	48	0	0
T232	25755	298	0	0
T234	12106	65	0	0
T266	5732	39	0	0
T267	18305	201	0	0
T273	10365	24	0	0
T274	8052	5	0	0
T275	13194	9	0	0
T276	12758	14	0	0
T277	4241	3	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	973283728	2658	0	0
T207	10133	52	0	0
T232	25755	318	0	0
T234	12106	16	0	0
T266	5732	29	0	0
T267	18305	206	0	0
T272	4895	3	0	0
T273	10365	23	0	0
T275	13194	43	0	0
T276	12758	59	0	0
T277	4241	2	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	973283728	2605	0	0
T207	10133	86	0	0
T232	25755	227	0	0
T234	12106	48	0	0
T267	18305	173	0	0
T272	4895	33	0	0
T273	10365	3	0	0
T274	8052	10	0	0
T275	13194	76	0	0
T276	12758	7	0	0
T277	4241	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	973283728	3712	0	0
T96	2010	8	0	0
T97	2325	29	0	0
T207	10133	64	0	0
T213	3045	13	0	0
T214	1721	1	0	0
T215	1916	6	0	0
T232	25755	554	0	0
T234	12106	12	0	0
T273	10365	39	0	0
T274	8052	9	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	973283728	2358	0	0
T207	10133	19	0	0
T232	25755	190	0	0
T234	12106	54	0	0
T266	5732	22	0	0
T267	18305	179	0	0
T273	10365	34	0	0
T274	8052	5	0	0
T275	13194	44	0	0
T276	12758	31	0	0
T277	4241	2	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	973283728	1629	0	0
T207	10133	37	0	0
T232	25755	100	0	0
T234	12106	36	0	0
T266	5732	11	0	0
T267	18305	186	0	0
T273	10365	21	0	0
T274	8052	20	0	0
T275	13194	15	0	0
T276	12758	51	0	0
T277	4241	5	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	973283728	2193	0	0
T207	10133	46	0	0
T232	25755	197	0	0
T234	12106	17	0	0
T267	18305	146	0	0
T272	4895	58	0	0
T273	10365	12	0	0
T274	8052	25	0	0
T275	13194	40	0	0
T276	12758	55	0	0
T277	4241	32	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	973283728	2826	0	0
T207	10133	67	0	0
T232	25755	159	0	0
T234	12106	72	0	0
T267	18305	185	0	0
T272	4895	8	0	0
T273	10365	2	0	0
T274	8052	53	0	0
T275	13194	39	0	0
T276	12758	80	0	0
T277	4241	55	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	973283728	2357	0	0
T207	10133	48	0	0
T232	25755	281	0	0
T234	12106	53	0	0
T266	5732	47	0	0
T267	18305	186	0	0
T273	10365	10	0	0
T274	8052	52	0	0
T275	13194	42	0	0
T276	12758	24	0	0
T277	4241	7	0	0