Unified Coverage Report :: Module :: usbdev

Module : usbdev

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.56	97.53	79.85	95.41		100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.56	97.53	79.85	95.41		100.00	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.56	97.53	79.85	95.41		100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.92	97.44	92.03	97.86	70.31	95.72	98.17

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_event	100.00	100.00				100.00
gen_no_stubbed_memory.u_memory_1p	98.96	95.83	100.00			100.00	100.00
gen_no_stubbed_memory.u_tlul2sram	85.93	86.78	75.84			81.11	100.00
i_usbdev_iomux	81.39	100.00	75.56			100.00	50.00
intr_av_out_empty	81.39	90.00	55.56			80.00	100.00
intr_av_overflow	81.25	100.00	25.00			100.00	100.00
intr_av_setup_empty	81.39	90.00	55.56			80.00	100.00
intr_disconnected	93.75	100.00	75.00			100.00	100.00
intr_frame	89.58	100.00	58.33			100.00	100.00
intr_host_lost	89.58	100.00	58.33			100.00	100.00
intr_hw_pkt_received	86.94	90.00	77.78			80.00	100.00
intr_hw_pkt_sent	86.94	90.00	77.78			80.00	100.00
intr_link_in_err	89.58	100.00	58.33			100.00	100.00
intr_link_out_err	89.58	100.00	58.33			100.00	100.00
intr_link_reset	89.58	100.00	58.33			100.00	100.00
intr_link_resume	89.58	100.00	58.33			100.00	100.00
intr_link_suspend	89.58	100.00	58.33			100.00	100.00
intr_powered	89.58	100.00	58.33			100.00	100.00
intr_rx_bitstuff_err	89.58	100.00	58.33			100.00	100.00
intr_rx_crc_err	93.75	100.00	75.00			100.00	100.00
intr_rx_full	73.06	90.00	22.22			80.00	100.00
intr_rx_pid_err	89.58	100.00	58.33			100.00	100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_ctr_errors	57.70	84.21	33.33			55.56
u_ctr_in	51.16	78.95	20.00			54.55
u_ctr_nodata_in	52.92	84.21	20.00			54.55
u_ctr_out	51.16	78.95	20.00			54.55
u_reg	97.70	98.85	97.70	100.00		98.41	93.55
usbdev_avoutfifo	96.32	100.00	85.29			100.00	100.00
usbdev_avsetupfifo	96.32	100.00	85.29			100.00	100.00
usbdev_csr_assert	100.00						100.00
usbdev_impl	89.86	95.90	91.55		70.31	91.54	100.00
usbdev_rxfifo	89.47	95.12	77.78			85.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : usbdev

	Line No.	Total	Covered	Percent
TOTAL		162	158	97.53
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	220	1	1	100.00
ALWAYS	222	5	5	100.00
CONT_ASSIGN	257	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	327	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	353	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	356	1	1	100.00
CONT_ASSIGN	360	1	0	0.00
ALWAYS	383	0	0
ALWAYS	383	3	3	100.00
ALWAYS	391	0	0
ALWAYS	391	4	4	100.00
ALWAYS	400	0	0
ALWAYS	400	3	3	100.00
ALWAYS	407	0	0
ALWAYS	407	3	3	100.00
ALWAYS	414	0	0
ALWAYS	414	3	3	100.00
ALWAYS	421	0	0
ALWAYS	421	2	2	100.00
ALWAYS	434	5	5	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	443	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	448	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	451	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	457	1	1	100.00
CONT_ASSIGN	458	1	1	100.00
CONT_ASSIGN	460	1	1	100.00
ALWAYS	464	3	3	100.00
ALWAYS	471	0	0
ALWAYS	471	3	3	100.00
ALWAYS	480	3	3	100.00
ALWAYS	492	3	3	100.00
ALWAYS	499	0	0
ALWAYS	499	3	3	100.00
ALWAYS	506	10	10	100.00
ALWAYS	525	3	3	100.00
ALWAYS	532	0	0
ALWAYS	532	3	3	100.00
ALWAYS	540	0	0
ALWAYS	540	3	3	100.00
ALWAYS	549	0	0
ALWAYS	549	3	3	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	560	1	1	100.00
CONT_ASSIGN	561	1	1	100.00
CONT_ASSIGN	684	1	1	100.00
CONT_ASSIGN	685	1	1	100.00
CONT_ASSIGN	687	1	1	100.00
CONT_ASSIGN	688	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
ALWAYS	715	0	0
ALWAYS	715	8	8	100.00
CONT_ASSIGN	800	1	1	100.00
CONT_ASSIGN	801	1	1	100.00
CONT_ASSIGN	802	1	1	100.00
CONT_ASSIGN	803	1	1	100.00
CONT_ASSIGN	811	1	1	100.00
ALWAYS	820	8	8	100.00
CONT_ASSIGN	834	1	1	100.00
CONT_ASSIGN	835	0	0
CONT_ASSIGN	838	1	1	100.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	896	1	1	100.00
CONT_ASSIGN	897	1	1	100.00
CONT_ASSIGN	901	1	1	100.00
CONT_ASSIGN	1164	1	1	100.00
CONT_ASSIGN	1165	1	1	100.00
CONT_ASSIGN	1166	1	1	100.00
CONT_ASSIGN	1167	1	1	100.00
CONT_ASSIGN	1207	1	1	100.00
CONT_ASSIGN	1210	1	1	100.00
CONT_ASSIGN	1219	1	1	100.00
ALWAYS	1222	5	5	100.00
ALWAYS	1231	3	3	100.00
CONT_ASSIGN	1244	1	1	100.00
CONT_ASSIGN	1247	1	1	100.00
CONT_ASSIGN	1254	1	1	100.00
ALWAYS	1258	3	3	100.00
CONT_ASSIGN	1265	1	1	100.00
CONT_ASSIGN	1270	1	1	100.00
CONT_ASSIGN	1272	1	1	100.00
CONT_ASSIGN	1280	1	1	100.00
CONT_ASSIGN	1282	1	1	100.00
CONT_ASSIGN	1284	1	1	100.00
CONT_ASSIGN	1286	1	1	100.00
CONT_ASSIGN	1296	1	0	0.00
CONT_ASSIGN	1300	1	0	0.00
CONT_ASSIGN	1303	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
123	1	1
167	1	1
220	1	1
222	1	1
223	1	1
225	1	1
226	1	1
228	1	1
257	1	1
258	1	1
259	1	1
263	1	1
264	1	1
266	1	1
268	1	1
316	1	1
321	1	1
324	1	1
327	1	1
352	1	1
353	1	1
354	1	1
355	1	1
356	1	1
360	0	1
383	1	1
384	1	1
385	1	1
391	1	1
392	1	1
393	1	1
394	1	1
400	1	1
401	1	1
402	1	1
407	1	1
408	1	1
409	1	1
414	1	1
415	1	1
416	1	1
421	1	1
422	1	1
434	1	1
435	1	1
436	1	1
438	1	1
439	1	1
442	1	1
443	1	1
447	1	1
448	1	1
449	1	1
451	1	1
456	1	1
457	1	1
458	1	1
460	1	1
464	1	1
465	1	1
466	1	1
			MISSING_ELSE
471	1	1
472	1	1
473	1	1
480	1	1
481	1	1
482	1	1
492	1	1
493	1	1
494	1	1
			MISSING_ELSE
499	1	1
500	1	1
501	1	1
506	1	1
507	1	1
508	1	1
509	1	1
510	1	1
512	1	1
514	1	1
515	1	1
516	1	1
518	1	1
			MISSING_ELSE
525	1	1
526	2	2
			MISSING_ELSE
532	1	1
533	1	1
534	1	1
540	1	1
541	1	1
542	1	1
549	1	1
550	1	1
551	1	1
559	1	1
560	1	1
561	1	1
684	1	1
685	1	1
687	1	1
688	1	1
706	1	1
709	1	1
715	1	1
716	1	1
717	1	1
718	1	1
719	1	1
720	1	1
722	1	1
723	1	1
800	1	1
801	1	1
802	1	1
803	1	1
811	1	1
820	1	1
821	1	1
822	1	1
823	1	1
825	1	1
826	1	1
828	1	1
829	1	1
			MISSING_ELSE
834	1	1
835		unreachable
838	1	1
839	1	1
896	1	1
897	1	1
901	1	1
1164	1	1
1165	1	1
1166	1	1
1167	1	1
1207	1	1
1210	1	1
1219	1	1
1222	1	1
1223	1	1
1224	1	1
1225	1	1
1226	1	1
			MISSING_ELSE
1231	1	1
1232	1	1
1234	1	1
1244	1	1
1247	1	1
1254	1	1
1258	1	1
1259	1	1
1261	1	1
1265	1	1
1270	1	1
1272	1	1
1280	1	1
1282	1	1
1284	1	1
1286	1	1
1296	0	1
1300	0	1
1303	0	1

---

Cond Coverage for Module : usbdev

	Total	Covered	Percent
Conditions	134	107	79.85
Logical	134	107	79.85
Non-Logical	0	0
Event	0	0

 LINE       167
 EXPRESSION (event_rx_crc5_err | event_rx_crc16_err)
             --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T40,T76,T74
1	0	Covered	T56,T57,T58

 LINE       220
 EXPRESSION (ns_cnt == 6'd47)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       257
 EXPRESSION (reg2hw.fifo_ctrl.avsetup_rst.qe & reg2hw.fifo_ctrl.avsetup_rst.q)
             ---------------1---------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T85,T86,T87
1	0	Covered	T85,T86,T87
1	1	Covered	T85,T86,T87

 LINE       258
 EXPRESSION (reg2hw.fifo_ctrl.avout_rst.qe & reg2hw.fifo_ctrl.avout_rst.q)
             --------------1--------------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T85,T86,T87
1	0	Covered	T85,T86,T87
1	1	Covered	T85,T86,T87

 LINE       259
 EXPRESSION (reg2hw.fifo_ctrl.rx_rst.qe & reg2hw.fifo_ctrl.rx_rst.q)
             -------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T85,T86,T87
1	1	Not Covered

 LINE       263
 EXPRESSION (connect_en & ((~avsetup_rvalid)))
             -----1----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T35,T14
1	1	Covered	T1,T2,T3

 LINE       264
 EXPRESSION (connect_en & ((~avout_rvalid)))
             -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       266
 EXPRESSION ((reg2hw.avsetupbuffer.qe & ((~avsetup_fifo_wready))) | (reg2hw.avoutbuffer.qe & ((~avout_fifo_wready))))
             --------------------------1-------------------------   ------------------------2-----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       266
 SUB-EXPRESSION (reg2hw.avsetupbuffer.qe & ((~avsetup_fifo_wready)))
                 -----------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T35,T14
1	1	Not Covered

 LINE       266
 SUB-EXPRESSION (reg2hw.avoutbuffer.qe & ((~avout_fifo_wready)))
                 ----------1----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       268
 EXPRESSION (connect_en & ((~rx_fifo_rvalid)))
             -----1----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T25,T26
1	1	Covered	T1,T2,T3

 LINE       316
 EXPRESSION (reg2hw.rxfifo.ep.re | reg2hw.rxfifo.setup.re | reg2hw.rxfifo.size.re | reg2hw.rxfifo.buffer.re)
             ---------1---------   -----------2----------   ----------3----------   -----------4-----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Not Covered
1	0	0	0	Not Covered

 LINE       327
 EXPRESSION (rx_wready & (rx_depth < 4'((RXFifoDepth - 1))))
             ----1----   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       442
 EXPRESSION (in_xact_starting ? in_buf[in_xact_start_ep] : in_buf_q)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T25,T27,T28

 LINE       443
 EXPRESSION (in_xact_starting ? in_size[in_xact_start_ep] : in_size_q)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T25,T27,T28

 LINE       447
 EXPRESSION (reg2hw.out_data_toggle.status.qe & reg2hw.out_data_toggle.mask.qe)
             ----------------1---------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T27,T36,T37

 LINE       456
 EXPRESSION (reg2hw.in_data_toggle.status.qe & reg2hw.in_data_toggle.mask.qe)
             ---------------1---------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T27,T36,T37

 LINE       465
 EXPRESSION (in_ep_xact_end && in_endpoint_val)
             -------1------    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T25,T27,T33

 LINE       493
 EXPRESSION (rx_wvalid && out_endpoint_val)
             ----1----    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T25,T26

 LINE       512
 EXPRESSION (setup_received & out_endpoint_val)
             -------1------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T29,T35,T14

 LINE       516
 EXPRESSION (in_ep_xact_end & in_endpoint_val)
             -------1------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T25,T27,T33

 LINE       542
 EXPRESSION (reg2hw.configin[i].rdy.q | reg2hw.configin[i].pend.q)
             ------------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T65,T194,T136
1	0	Covered	T25,T27,T28

 LINE       550
 EXPRESSION (set_sending[i] | set_sentbit[i] | update_pend[i])
             -------1------   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T25,T27,T33
1	0	0	Covered	T25,T27,T28

 LINE       551
 EXPRESSION (((~set_sentbit[i])) & ((~update_pend[i])))
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T25,T27,T33
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       560
 EXPRESSION (cfg_pinflip ? 1'b0 : usb_pullup_en)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T13,T55

 LINE       561
 EXPRESSION (((!cfg_pinflip)) ? 1'b0 : usb_pullup_en)
             --------1-------

-1-	Status	Tests
0	Covered	T11,T13,T55
1	Covered	T1,T2,T3

 LINE       688
 EXPRESSION (reg2hw.usbctrl.resume_link_active.qe & reg2hw.usbctrl.resume_link_active.q)
             ------------------1-----------------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       800
 EXPRESSION (usb_mem_b_req | sw_mem_a_req)
             ------1------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T26,T27
1	0	Covered	T1,T2,T3

 LINE       801
 EXPRESSION (usb_mem_b_req ? usb_mem_b_write : sw_mem_a_write)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       802
 EXPRESSION (usb_mem_b_req ? usb_mem_b_addr : sw_mem_a_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       803
 EXPRESSION (usb_mem_b_req ? usb_mem_b_wdata : sw_mem_a_wdata)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       826
 EXPRESSION (usb_mem_b_req & ((!usb_mem_b_write)))
             ------1------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T25,T27,T28

 LINE       834
 EXPRESSION (gen_no_stubbed_memory.mem_rvalid & ((!gen_no_stubbed_memory.mem_rsteering)))
             ----------------1---------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T25,T27,T28
1	1	Covered	T2,T26,T27

 LINE       839
 EXPRESSION (gen_no_stubbed_memory.mem_b_read_q ? gen_no_stubbed_memory.mem_rdata : gen_no_stubbed_memory.mem_b_rdata_q)
             -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T25,T27,T28

 LINE       901
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       1210
 EXPRESSION (use_diff_rcvr & ((~link_suspend)))
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T38,T4,T5
1	1	Covered	T1,T2,T3

 LINE       1219
 EXPRESSION (usb_rcvr_ok_counter_q == '0)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1223
 EXPRESSION (use_diff_rcvr & ((!usb_rx_enable_o)))
             ------1------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T38,T4,T19

 LINE       1225
 EXPRESSION (us_tick && (usb_rcvr_ok_counter_q > '0))
             ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T200,T201,T202

 LINE       1247
 EXPRESSION (usb_ref_disable ? 1'b0 : event_sof)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T18,T49,T203

 LINE       1254
 EXPRESSION (usb_ref_pulse_o ? 1'b1 : ((((!link_active)) || host_lost || usb_ref_disable) ? 1'b0 : usb_ref_val_q))
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T18,T48,T49

 LINE       1254
 SUB-EXPRESSION ((((!link_active)) || host_lost || usb_ref_disable) ? 1'b0 : usb_ref_val_q)
                 -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1254
 SUB-EXPRESSION (((!link_active)) || host_lost || usb_ref_disable)
                 --------1-------    ----2----    -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T18,T49,T203
0	1	0	Covered	T34,T50,T51
1	0	0	Covered	T1,T2,T3

 LINE       1270
 EXPRESSION (reg2hw.wake_control.suspend_req.qe & reg2hw.wake_control.suspend_req.q)
             -----------------1----------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       1272
 EXPRESSION (reg2hw.wake_control.wake_ack.qe & reg2hw.wake_control.wake_ack.q)
             ---------------1---------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       1309
 EXPRESSION (reg2hw.count_out.rst.qe & reg2hw.count_out.rst.q)
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       1335
 EXPRESSION (reg2hw.count_in.rst.qe & reg2hw.count_in.rst.q)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       1358
 EXPRESSION (reg2hw.count_nodata_in.rst.qe & reg2hw.count_nodata_in.rst.q)
             --------------1--------------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       1375
 EXPRESSION (reg2hw.count_errors.rst.qe & reg2hw.count_errors.rst.q)
             -------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

---

Toggle Coverage for Module : usbdev

	Total	Covered	Percent
Totals	72	68	94.44
Total Bits	436	416	95.41
Total Bits 0->1	218	208	95.41
Total Bits 1->0	218	208	95.41

Ports	72	68	94.44
Port Bits	436	416	95.41
Port Bits 0->1	218	208	95.41
Port Bits 1->0	218	208	95.41

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T204,T205,T206	Yes	T1,T2,T3	INPUT
clk_aon_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_aon_ni	Yes	Yes	T204,T205,T206	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T27	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T25,T31	Yes	T1,T25,T31	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T207,T208,T209	Yes	T207,T208,T209	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T2,T25,T26	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT
cio_usb_dp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_usb_dn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
usb_rx_d_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_usb_dp_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cio_usb_dp_en_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cio_usb_dn_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cio_usb_dn_en_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
usb_tx_se0_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
usb_tx_d_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cio_sense_i	Yes	Yes	T7,T8,T48	Yes	T1,T2,T3	INPUT
usb_dp_pullup_o	Yes	Yes	T4,T19,T5	Yes	T1,T2,T3	OUTPUT
usb_dn_pullup_o	Yes	Yes	T11,T13,T55	Yes	T11,T13,T55	OUTPUT
usb_rx_enable_o	Yes	Yes	T38,T4,T19	Yes	T1,T2,T3	OUTPUT
usb_tx_use_d_se0_o	Yes	Yes	T207,T210,T211	Yes	T207,T210,T212	OUTPUT
usb_aon_suspend_req_o	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
usb_aon_wake_ack_o	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
usb_aon_bus_reset_i	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	INPUT
usb_aon_sense_lost_i	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	INPUT
usb_aon_bus_not_idle_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
usb_aon_wake_detect_active_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
usb_ref_val_o	Yes	Yes	T18,T48,T49	Yes	T18,T48,T49	OUTPUT
usb_ref_pulse_o	Yes	Yes	T18,T48,T49	Yes	T18,T48,T49	OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
intr_pkt_received_o	Yes	Yes	T26,T72,T73	Yes	T26,T72,T73	OUTPUT
intr_pkt_sent_o	Yes	Yes	T25,T33,T38	Yes	T25,T33,T38	OUTPUT
intr_powered_o	Yes	Yes	T96,T98,T99	Yes	T96,T98,T99	OUTPUT
intr_disconnected_o	Yes	Yes	T48,T52,T53	Yes	T48,T52,T53	OUTPUT
intr_host_lost_o	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
intr_link_reset_o	Yes	Yes	T97,T99,T213	Yes	T97,T99,T213	OUTPUT
intr_link_suspend_o	Yes	Yes	T96,T97,T99	Yes	T96,T97,T99	OUTPUT
intr_link_resume_o	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
intr_av_out_empty_o	Yes	Yes	T97,T214,T213	Yes	T97,T214,T213	OUTPUT
intr_rx_full_o	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
intr_av_overflow_o	Yes	Yes	T97,T99,T215	Yes	T97,T99,T215	OUTPUT
intr_link_in_err_o	Yes	Yes	T96,T98,T99	Yes	T96,T98,T99	OUTPUT
intr_link_out_err_o	Yes	Yes	T96,T98,T99	Yes	T96,T98,T99	OUTPUT
intr_rx_crc_err_o	Yes	Yes	T56,T57,T58	Yes	T56,T57,T58	OUTPUT
intr_rx_pid_err_o	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
intr_rx_bitstuff_err_o	Yes	Yes	T97,T99,T215	Yes	T97,T99,T215	OUTPUT
intr_frame_o	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
intr_av_setup_empty_o	Yes	Yes	T96,T97,T99	Yes	T96,T97,T99	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : usbdev

	Line No.	Total	Covered	Percent
Branches		48	48	100.00
TERNARY	442	2	2	100.00
TERNARY	443	2	2	100.00
TERNARY	560	2	2	100.00
TERNARY	561	2	2	100.00
TERNARY	1247	2	2	100.00
TERNARY	1254	3	3	100.00
TERNARY	801	2	2	100.00
TERNARY	802	2	2	100.00
TERNARY	803	2	2	100.00
TERNARY	839	2	2	100.00
IF	222	3	3	100.00
IF	434	2	2	100.00
IF	465	2	2	100.00
IF	493	2	2	100.00
IF	508	4	4	100.00
IF	526	2	2	100.00
IF	718	2	2	100.00
IF	1223	3	3	100.00
IF	1231	2	2	100.00
IF	1258	2	2	100.00
IF	820	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	442	(in_xact_starting) ? 

Branches:

-1-	Status	Tests
1	Covered	T25,T27,T28
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	443	(in_xact_starting) ? 

Branches:

-1-	Status	Tests
1	Covered	T25,T27,T28
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	560	(cfg_pinflip) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T13,T55
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	561	((!cfg_pinflip)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T11,T13,T55

	LineNo.	Expression
-1-:	1247	(usb_ref_disable) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T49,T203
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1254	(usb_ref_pulse_o) ? 
-2-:	1254	((((!link_active) || host_lost) || usb_ref_disable)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T48,T49
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	801	(usb_mem_b_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	802	(usb_mem_b_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	803	(usb_mem_b_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	839	(gen_no_stubbed_memory.mem_b_read_q) ? 

Branches:

-1-	Status	Tests
1	Covered	T25,T27,T28
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	222	if ((!rst_n))
-2-:	225	if (us_tick)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	434	if ((!rst_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	465	if ((in_ep_xact_end && in_endpoint_val))

Branches:

-1-	Status	Tests
1	Covered	T25,T27,T33
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	493	if ((rx_wvalid && out_endpoint_val))

Branches:

-1-	Status	Tests
1	Covered	T2,T25,T26
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	508	if (event_link_reset)
-2-:	512	if ((setup_received & out_endpoint_val))
-3-:	516	if ((in_ep_xact_end & in_endpoint_val))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T29,T35,T14
0	0	1	Covered	T25,T27,T33
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	526	if (in_xact_starting)

Branches:

-1-	Status	Tests
1	Covered	T25,T27,T28
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	718	if (((setup_received && out_endpoint_val) && (out_endpoint == 4'((unsigned'(i))))))

Branches:

-1-	Status	Tests
1	Covered	T29,T35,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1223	if ((use_diff_rcvr & (!usb_rx_enable_o)))
-2-:	1225	if ((us_tick && (usb_rcvr_ok_counter_q > '0)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T38,T4,T19
0	1	Covered	T200,T201,T202
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1231	if ((!rst_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1258	if ((!rst_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	820	if ((!rst_ni))
-2-:	828	if (gen_no_stubbed_memory.mem_b_read_q)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T25,T27,T28
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : usbdev

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	35	35	100.00	35	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	35	35	100.00	35	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertsKnown_A	971304041	971159700	0	0
CIODnEnKnown_A	971304041	971159700	0	0
CIODnKnown_A	971304041	971159700	0	0
CIODpEnKnown_A	971304041	971159700	0	0
CIODpKnown_A	971304041	971159700	0	0
FpvSecCmRegWeOnehotCheck_A	971304041	60	0	0
TlOAReadyKnown_A	971304041	971159700	0	0
TlODValidKnown_A	971304041	971159700	0	0
USBAonSuspendReqKnown_A	971304041	971159700	0	0
USBAonWakeAckKnown_A	971304041	971159700	0	0
USBDnPUKnown_A	971304041	971159700	0	0
USBDpPUKnown_A	971304041	971159700	0	0
USBIntrAvOutEmptyKnown_A	971304041	971159700	0	0
USBIntrAvOverKnown_A	971304041	971159700	0	0
USBIntrAvSetupEmptyKnown_A	971304041	971159700	0	0
USBIntrDisConKnown_A	971304041	971159700	0	0
USBIntrFrameKnown_A	971304041	971159700	0	0
USBIntrHostLostKnown_A	971304041	971159700	0	0
USBIntrLinkInErrKnown_A	971304041	971159700	0	0
USBIntrLinkOutErrKnown_A	971304041	971159700	0	0
USBIntrLinkResKnown_A	971304041	971159700	0	0
USBIntrLinkRstKnown_A	971304041	971159700	0	0
USBIntrLinkSusKnown_A	971304041	971159700	0	0
USBIntrPktRcvdKnown_A	971304041	971159700	0	0
USBIntrPktSentKnown_A	971304041	971159700	0	0
USBIntrPwrdKnown_A	971304041	971159700	0	0
USBIntrRxBitstuffErrKnown_A	971304041	971159700	0	0
USBIntrRxCrCErrKnown_A	971304041	971159700	0	0
USBIntrRxFullKnown_A	971304041	971159700	0	0
USBIntrRxPidErrKnown_A	971304041	971159700	0	0
USBRefPulseKnown_A	971304041	971159700	0	0
USBRefValKnown_A	971304041	971159700	0	0
USBRxEnableKnown_A	971304041	971159700	0	0
USBTxDKnown_A	971304041	971159700	0	0
USBTxSe0Known_A	971304041	971159700	0	0

AlertsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

CIODnEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

CIODnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

CIODpEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

CIODpKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	60	0	0
T204	16404	10	0	0
T205	0	10	0	0
T206	0	10	0	0
T216	0	10	0	0
T217	0	20	0	0
T218	537418	0	0	0
T219	638948	0	0	0
T220	485665	0	0	0
T221	636772	0	0	0
T222	481856	0	0	0
T223	487174	0	0	0
T224	484270	0	0	0
T225	482555	0	0	0
T226	482405	0	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

USBAonSuspendReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

USBAonWakeAckKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

USBDnPUKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

USBDpPUKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

USBIntrAvOutEmptyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

USBIntrAvOverKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

USBIntrAvSetupEmptyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

USBIntrDisConKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

USBIntrFrameKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

USBIntrHostLostKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

USBIntrLinkInErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

USBIntrLinkOutErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

USBIntrLinkResKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

USBIntrLinkRstKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

USBIntrLinkSusKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

USBIntrPktRcvdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

USBIntrPktSentKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

USBIntrPwrdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

USBIntrRxBitstuffErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

USBIntrRxCrCErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

USBIntrRxFullKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

USBIntrRxPidErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

USBRefPulseKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

USBRefValKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

USBRxEnableKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

USBTxDKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

USBTxSe0Known_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0