Unified Coverage Report :: Module Instance :: tb.dut.usbdev_avsetupfifo

Module Instance : tb.dut.usbdev_avsetupfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.07	100.00	64.29			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	100.00	85.29			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.56	97.53	79.85	95.41		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.usbdev_avoutfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.07	100.00	64.29			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	100.00	85.29			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.56	97.53	79.85	95.41		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.usbdev_rxfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.62	100.00	62.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.47	95.12	77.78			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.56	97.53	79.85	95.41		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	86.51	92.59	90.00			76.92

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.42	98.55	78.81			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.62	100.00	62.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.64	95.00	72.22			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.42	98.55	78.81			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.32	95.00	77.27			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.42	98.55	78.81			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Line Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Covered	Percent
Conditions	14	9	64.29
Logical	14	9	64.29
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T85,T86,T87
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T29,T35,T14

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T29,T35,T14

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T29,T35,T14
1	1	0	Not Covered
1	1	1	Covered	T29,T35,T14

---

Branch Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T29,T35,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	971304041	622125	0	0
DepthKnown_A	971304041	971159700	0	0
RvalidKnown_A	971304041	971159700	0	0
WreadyKnown_A	971304041	971159700	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	971304041	622125	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	622125	0	0
T14	0	549	0	0
T17	0	557	0	0
T29	485608	561	0	0
T30	485273	0	0	0
T31	484294	0	0	0
T32	486345	0	0	0
T33	521367	0	0	0
T34	120084	0	0	0
T35	0	564	0	0
T41	483296	0	0	0
T42	484115	0	0	0
T65	0	2121	0	0
T66	0	561	0	0
T82	483999	0	0	0
T83	484515	0	0	0
T85	0	4531	0	0
T86	0	2411	0	0
T88	0	549	0	0
T89	0	554	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	622125	0	0
T14	0	549	0	0
T17	0	557	0	0
T29	485608	561	0	0
T30	485273	0	0	0
T31	484294	0	0	0
T32	486345	0	0	0
T33	521367	0	0	0
T34	120084	0	0	0
T35	0	564	0	0
T41	483296	0	0	0
T42	484115	0	0	0
T65	0	2121	0	0
T66	0	561	0	0
T82	483999	0	0	0
T83	484515	0	0	0
T85	0	4531	0	0
T86	0	2411	0	0
T88	0	549	0	0
T89	0	554	0	0

Line Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Covered	Percent
Conditions	14	9	64.29
Logical	14	9	64.29
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T85,T86,T87
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T2,T25,T26

---

Branch Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	971304041	26101455	0	0
DepthKnown_A	971304041	971159700	0	0
RvalidKnown_A	971304041	971159700	0	0
WreadyKnown_A	971304041	971159700	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	971304041	26101455	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	26101455	0	0
T1	485016	1795	0	0
T2	485220	1793	0	0
T3	482990	1448	0	0
T25	487826	2182	0	0
T26	484436	688	0	0
T27	525289	18848	0	0
T28	483678	0	0	0
T29	485608	0	0	0
T30	0	1755	0	0
T39	484687	2380	0	0
T40	481933	1104	0	0
T82	0	2361	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	26101455	0	0
T1	485016	1795	0	0
T2	485220	1793	0	0
T3	482990	1448	0	0
T25	487826	2182	0	0
T26	484436	688	0	0
T27	525289	18848	0	0
T28	483678	0	0	0
T29	485608	0	0	0
T30	0	1755	0	0
T39	484687	2380	0	0
T40	481933	1104	0	0
T82	0	2361	0	0

Line Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T25,T26

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T25,T26

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T25,T26
1	1	0	Not Covered
1	1	1	Covered	T2,T25,T26

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T25,T26
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T25,T26

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T25,T26
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	971304041	2466215	0	0
DepthKnown_A	971304041	971159700	0	0
RvalidKnown_A	971304041	971159700	0	0
WreadyKnown_A	971304041	971159700	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	971304041	2466215	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	2466215	0	0
T2	485220	100	0	0
T3	482990	0	0	0
T25	487826	98	0	0
T26	484436	81	0	0
T27	525289	1647	0	0
T28	483678	0	0	0
T29	485608	1063	0	0
T30	0	147	0	0
T32	0	1235	0	0
T39	484687	4	0	0
T40	481933	0	0	0
T42	0	107	0	0
T82	483999	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	2466215	0	0
T2	485220	100	0	0
T3	482990	0	0	0
T25	487826	98	0	0
T26	484436	81	0	0
T27	525289	1647	0	0
T28	483678	0	0	0
T29	485608	1063	0	0
T30	0	147	0	0
T32	0	1235	0	0
T39	484687	4	0	0
T40	481933	0	0	0
T42	0	107	0	0
T82	483999	4	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	973283728	7735600	0	0
DepthKnown_A	973283728	973084633	0	0
RvalidKnown_A	973283728	973084633	0	0
WreadyKnown_A	973283728	973084633	0	0
gen_passthru_fifo.paramCheckPass	2042	2042	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	973283728	7735600	0	0
T1	485016	3515	0	0
T2	485220	3496	0	0
T3	482990	3704	0	0
T25	487826	3707	0	0
T26	484436	3708	0	0
T27	525289	3797	0	0
T28	483678	3702	0	0
T29	485608	3480	0	0
T39	484687	3723	0	0
T40	481933	3565	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	973283728	973084633	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	973283728	973084633	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	973283728	973084633	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2042	2042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	973283728	13711357	0	0
DepthKnown_A	973283728	973084633	0	0
RvalidKnown_A	973283728	973084633	0	0
WreadyKnown_A	973283728	973084633	0	0
gen_passthru_fifo.paramCheckPass	2042	2042	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	973283728	13711357	0	0
T1	485016	10688	0	0
T2	485220	15359	0	0
T3	482990	3704	0	0
T25	487826	3707	0	0
T26	484436	3708	0	0
T27	525289	16706	0	0
T28	483678	3702	0	0
T29	485608	15206	0	0
T39	484687	3723	0	0
T40	481933	3565	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	973283728	973084633	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	973283728	973084633	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	973283728	973084633	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2042	2042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	973283728	391277	0	0
DepthKnown_A	973283728	973084633	0	0
RvalidKnown_A	973283728	973084633	0	0
WreadyKnown_A	973283728	973084633	0	0
gen_passthru_fifo.paramCheckPass	2042	2042	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	973283728	391277	0	0
T2	485220	12	0	0
T3	482990	0	0	0
T25	487826	0	0	0
T26	484436	3	0	0
T27	525289	116	0	0
T28	483678	0	0	0
T29	485608	0	0	0
T33	0	112	0	0
T34	0	7244	0	0
T39	484687	16	0	0
T40	481933	0	0	0
T42	0	15	0	0
T72	0	2	0	0
T82	483999	16	0	0
T83	0	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	973283728	973084633	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	973283728	973084633	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	973283728	973084633	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2042	2042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	973283728	638883	0	0
DepthKnown_A	973283728	973084633	0	0
RvalidKnown_A	973283728	973084633	0	0
WreadyKnown_A	973283728	973084633	0	0
gen_passthru_fifo.paramCheckPass	2042	2042	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	973283728	638883	0	0
T2	485220	36	0	0
T3	482990	0	0	0
T25	487826	0	0	0
T26	484436	3	0	0
T27	525289	583	0	0
T28	483678	0	0	0
T29	485608	0	0	0
T33	0	112	0	0
T34	0	7244	0	0
T39	484687	16	0	0
T40	481933	0	0	0
T42	0	66	0	0
T72	0	2	0	0
T82	483999	16	0	0
T83	0	72	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	973283728	973084633	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	973283728	973084633	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	973283728	973084633	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2042	2042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	973283728	7291387	0	0
DepthKnown_A	973283728	973084633	0	0
RvalidKnown_A	973283728	973084633	0	0
WreadyKnown_A	973283728	973084633	0	0
gen_passthru_fifo.paramCheckPass	2042	2042	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	973283728	7291387	0	0
T1	485016	3515	0	0
T2	485220	3484	0	0
T3	482990	3704	0	0
T25	487826	3707	0	0
T26	484436	3705	0	0
T27	525289	3681	0	0
T28	483678	3702	0	0
T29	485608	3480	0	0
T39	484687	3707	0	0
T40	481933	3565	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	973283728	973084633	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	973283728	973084633	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	973283728	973084633	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2042	2042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	973283728	13072474	0	0
DepthKnown_A	973283728	973084633	0	0
RvalidKnown_A	973283728	973084633	0	0
WreadyKnown_A	973283728	973084633	0	0
gen_passthru_fifo.paramCheckPass	2042	2042	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	973283728	13072474	0	0
T1	485016	10688	0	0
T2	485220	15323	0	0
T3	482990	3704	0	0
T25	487826	3707	0	0
T26	484436	3705	0	0
T27	525289	16123	0	0
T28	483678	3702	0	0
T29	485608	15206	0	0
T39	484687	3707	0	0
T40	481933	3565	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	973283728	973084633	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	973283728	973084633	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	973283728	973084633	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2042	2042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T26,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T26,T27

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T26,T27

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T27,T42
1	1	0	Not Covered
1	1	1	Covered	T2,T26,T27

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T26,T27
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T26,T27

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T26,T27
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	971304041	580452	0	0
DepthKnown_A	971304041	971159700	0	0
RvalidKnown_A	971304041	971159700	0	0
WreadyKnown_A	971304041	971159700	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	971304041	580452	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	580452	0	0
T2	485220	36	0	0
T3	482990	0	0	0
T25	487826	0	0	0
T26	484436	3	0	0
T27	525289	583	0	0
T28	483678	0	0	0
T29	485608	0	0	0
T33	0	112	0	0
T34	0	7244	0	0
T39	484687	16	0	0
T40	481933	0	0	0
T42	0	66	0	0
T72	0	2	0	0
T82	483999	16	0	0
T83	0	72	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	580452	0	0
T2	485220	36	0	0
T3	482990	0	0	0
T25	487826	0	0	0
T26	484436	3	0	0
T27	525289	583	0	0
T28	483678	0	0	0
T29	485608	0	0	0
T33	0	112	0	0
T34	0	7244	0	0
T39	484687	16	0	0
T40	481933	0	0	0
T42	0	66	0	0
T72	0	2	0	0
T82	483999	16	0	0
T83	0	72	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T26,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T26,T27

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T26,T27

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T26,T27

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T26,T27
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T26,T27

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T26,T27
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	971304041	213555	0	0
DepthKnown_A	971304041	971159700	0	0
RvalidKnown_A	971304041	971159700	0	0
WreadyKnown_A	971304041	971159700	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	971304041	213555	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	213555	0	0
T2	485220	12	0	0
T3	482990	0	0	0
T25	487826	0	0	0
T26	484436	3	0	0
T27	525289	116	0	0
T28	483678	0	0	0
T29	485608	0	0	0
T33	0	112	0	0
T34	0	4376	0	0
T39	484687	16	0	0
T40	481933	0	0	0
T42	0	15	0	0
T72	0	2	0	0
T82	483999	16	0	0
T83	0	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	213555	0	0
T2	485220	12	0	0
T3	482990	0	0	0
T25	487826	0	0	0
T26	484436	3	0	0
T27	525289	116	0	0
T28	483678	0	0	0
T29	485608	0	0	0
T33	0	112	0	0
T34	0	4376	0	0
T39	484687	16	0	0
T40	481933	0	0	0
T42	0	15	0	0
T72	0	2	0	0
T82	483999	16	0	0
T83	0	16	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T27,T42
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T26,T27

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T26,T27

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T27,T42
1	1	0	Not Covered
1	1	1	Covered	T2,T26,T27

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T26,T27

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T26,T27

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T27,T42
1	0	Covered	T2,T26,T27
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T26,T27
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T26,T27
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T26,T27

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T26,T27
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	971304041	353300	0	0
DepthKnown_A	971304041	971159700	0	0
RvalidKnown_A	971304041	971159700	0	0
WreadyKnown_A	971304041	971159700	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	971304041	353300	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	353300	0	0
T2	485220	36	0	0
T3	482990	0	0	0
T25	487826	0	0	0
T26	484436	3	0	0
T27	525289	583	0	0
T28	483678	0	0	0
T29	485608	0	0	0
T33	0	112	0	0
T34	0	4376	0	0
T39	484687	16	0	0
T40	481933	0	0	0
T42	0	66	0	0
T72	0	2	0	0
T82	483999	16	0	0
T83	0	72	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	971159700	0	0
T1	485016	484959	0	0
T2	485220	485137	0	0
T3	482990	482940	0	0
T25	487826	487752	0	0
T26	484436	484347	0	0
T27	525289	525190	0	0
T28	483678	483590	0	0
T29	485608	485556	0	0
T39	484687	484620	0	0
T40	481933	481866	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	971304041	353300	0	0
T2	485220	36	0	0
T3	482990	0	0	0
T25	487826	0	0	0
T26	484436	3	0	0
T27	525289	583	0	0
T28	483678	0	0	0
T29	485608	0	0	0
T33	0	112	0	0
T34	0	4376	0	0
T39	484687	16	0	0
T40	481933	0	0	0
T42	0	66	0	0
T72	0	2	0	0
T82	483999	16	0	0
T83	0	72	0	0