Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	60987	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	61036	1		T1	111		T2	145		T3	21

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	75562	1		T1	82		T2	43		T3	92
values[0x0]	22618	1		T1	46		T2	44		T3	17
values[0x1]	23843	1		T1	39		T2	104		T3	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	42448	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	79575	1		T1	125		T2	179		T3	54

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	355	1		T1	1		T2	2		T6	1
valid_sources[0x01]	461	1		T2	2		T6	1		T4	6
valid_sources[0x02]	557	1		T1	1		T3	1		T6	1
valid_sources[0x03]	586	1		T1	2		T2	1		T8	1
valid_sources[0x04]	501	1		T6	1		T4	7		T13	4
valid_sources[0x05]	369	1		T1	3		T2	1		T4	3
valid_sources[0x06]	289	1		T1	1		T3	3		T6	1
valid_sources[0x07]	782	1		T2	4		T3	2		T6	1
valid_sources[0x08]	457	1		T3	2		T6	3		T4	9
valid_sources[0x09]	477	1		T2	3		T8	1		T4	10
valid_sources[0x0a]	500	1		T2	4		T6	2		T4	6
valid_sources[0x0b]	440	1		T2	1		T6	1		T4	1
valid_sources[0x0c]	406	1		T2	2		T3	2		T6	1
valid_sources[0x0d]	299	1		T1	2		T2	1		T6	2
valid_sources[0x0e]	394	1		T4	7		T31	16		T19	3
valid_sources[0x0f]	361	1		T1	3		T2	3		T3	1
valid_sources[0x10]	461	1		T1	1		T2	1		T6	1
valid_sources[0x11]	391	1		T2	3		T6	1		T8	1
valid_sources[0x12]	617	1		T1	4		T6	1		T4	4
valid_sources[0x13]	417	1		T3	6		T6	1		T8	6
valid_sources[0x14]	1001	1		T2	1		T3	2		T6	1
valid_sources[0x15]	353	1		T6	2		T16	1		T4	1
valid_sources[0x16]	423	1		T1	2		T3	5		T4	3
valid_sources[0x17]	393	1		T3	1		T6	1		T4	6
valid_sources[0x18]	469	1		T2	1		T6	2		T8	1
valid_sources[0x19]	390	1		T2	1		T6	1		T8	1
valid_sources[0x1a]	425	1		T6	2		T16	1		T4	1
valid_sources[0x1b]	296	1		T1	3		T6	2		T4	6
valid_sources[0x1c]	462	1		T1	1		T2	3		T3	1
valid_sources[0x1d]	786	1		T1	2		T6	1		T4	10
valid_sources[0x1e]	432	1		T1	2		T6	1		T4	6
valid_sources[0x1f]	501	1		T6	3		T4	3		T13	7
valid_sources[0x20]	571	1		T2	1		T6	1		T8	4
valid_sources[0x21]	558	1		T2	1		T6	1		T16	1
valid_sources[0x22]	586	1		T1	1		T6	1		T4	7
valid_sources[0x23]	429	1		T3	1		T6	3		T4	4
valid_sources[0x24]	461	1		T2	1		T6	2		T4	6
valid_sources[0x25]	549	1		T2	1		T6	2		T8	12
valid_sources[0x26]	368	1		T2	2		T6	2		T4	11
valid_sources[0x27]	472	1		T1	1		T2	1		T6	1
valid_sources[0x28]	425	1		T1	2		T2	2		T3	1
valid_sources[0x29]	414	1		T2	2		T4	5		T13	4
valid_sources[0x2a]	382	1		T3	5		T13	1		T45	15
valid_sources[0x2b]	617	1		T2	3		T3	1		T6	1
valid_sources[0x2c]	524	1		T1	1		T3	1		T6	1
valid_sources[0x2d]	521	1		T6	2		T16	2		T4	5
valid_sources[0x2e]	496	1		T2	1		T3	3		T6	1
valid_sources[0x2f]	451	1		T1	1		T6	1		T4	5
valid_sources[0x30]	683	1		T6	3		T4	4		T9	128
valid_sources[0x31]	504	1		T1	3		T3	4		T8	3
valid_sources[0x32]	466	1		T2	1		T6	4		T16	2
valid_sources[0x33]	447	1		T1	2		T6	3		T4	8
valid_sources[0x34]	433	1		T1	1		T2	1		T8	9
valid_sources[0x35]	466	1		T1	2		T6	1		T4	5
valid_sources[0x36]	558	1		T6	3		T8	3		T4	9
valid_sources[0x37]	343	1		T2	1		T4	5		T13	41
valid_sources[0x38]	411	1		T1	1		T4	2		T13	2
valid_sources[0x39]	403	1		T2	1		T6	2		T4	1
valid_sources[0x3a]	336	1		T1	1		T6	2		T4	2
valid_sources[0x3b]	507	1		T6	5		T16	1		T4	2
valid_sources[0x3c]	508	1		T1	2		T2	1		T6	1
valid_sources[0x3d]	746	1		T1	1		T2	1		T3	4
valid_sources[0x3e]	395	1		T1	1		T2	1		T6	2
valid_sources[0x3f]	641	1		T1	2		T3	2		T16	1
valid_sources[0x40]	631	1		T3	2		T6	2		T8	2
valid_sources[0x41]	581	1		T1	2		T6	1		T4	7
valid_sources[0x42]	605	1		T3	1		T6	3		T4	5
valid_sources[0x43]	412	1		T2	1		T16	1		T4	6
valid_sources[0x44]	489	1		T1	1		T6	3		T4	9
valid_sources[0x45]	542	1		T3	1		T6	2		T4	6
valid_sources[0x46]	324	1		T4	1		T45	6		T31	28
valid_sources[0x47]	573	1		T1	1		T6	4		T8	1
valid_sources[0x48]	509	1		T1	1		T2	1		T6	1
valid_sources[0x49]	507	1		T6	1		T4	2		T9	124
valid_sources[0x4a]	435	1		T1	1		T3	1		T6	2
valid_sources[0x4b]	382	1		T3	1		T6	2		T4	10
valid_sources[0x4c]	604	1		T6	2		T4	4		T13	8
valid_sources[0x4d]	405	1		T2	1		T6	2		T4	2
valid_sources[0x4e]	334	1		T1	1		T2	1		T4	4
valid_sources[0x4f]	343	1		T1	2		T2	1		T6	3
valid_sources[0x50]	535	1		T3	5		T6	1		T4	8
valid_sources[0x51]	457	1		T1	2		T3	2		T6	1
valid_sources[0x52]	369	1		T1	2		T4	6		T13	10
valid_sources[0x53]	552	1		T6	1		T4	6		T9	116
valid_sources[0x54]	375	1		T4	5		T5	2		T13	3
valid_sources[0x55]	506	1		T1	2		T8	6		T4	4
valid_sources[0x56]	346	1		T1	2		T6	1		T13	13
valid_sources[0x57]	382	1		T2	3		T6	1		T4	6
valid_sources[0x58]	456	1		T1	1		T6	3		T4	9
valid_sources[0x59]	368	1		T6	1		T4	5		T13	16
valid_sources[0x5a]	511	1		T8	4		T4	3		T13	4
valid_sources[0x5b]	472	1		T2	2		T6	2		T4	13
valid_sources[0x5c]	472	1		T1	2		T2	2		T6	1
valid_sources[0x5d]	461	1		T1	1		T6	2		T4	8
valid_sources[0x5e]	517	1		T6	3		T8	8		T4	3
valid_sources[0x5f]	305	1		T2	1		T6	2		T4	1
valid_sources[0x60]	595	1		T1	2		T6	1		T16	1
valid_sources[0x61]	351	1		T1	2		T2	1		T3	5
valid_sources[0x62]	387	1		T1	1		T6	1		T4	8
valid_sources[0x63]	460	1		T1	3		T2	1		T3	2
valid_sources[0x64]	466	1		T1	1		T6	2		T4	5
valid_sources[0x65]	540	1		T16	1		T4	2		T13	12
valid_sources[0x66]	575	1		T1	1		T2	1		T6	2
valid_sources[0x67]	691	1		T2	1		T3	2		T6	1
valid_sources[0x68]	431	1		T1	1		T2	1		T6	1
valid_sources[0x69]	472	1		T2	2		T6	1		T8	2
valid_sources[0x6a]	454	1		T1	1		T2	1		T6	1
valid_sources[0x6b]	497	1		T2	1		T4	4		T13	6
valid_sources[0x6c]	374	1		T1	1		T6	1		T4	2
valid_sources[0x6d]	575	1		T6	1		T4	5		T13	11
valid_sources[0x6e]	398	1		T6	3		T8	1		T4	3
valid_sources[0x6f]	359	1		T6	2		T4	11		T13	9
valid_sources[0x70]	691	1		T6	1		T16	1		T4	1
valid_sources[0x71]	591	1		T4	5		T13	2		T31	34
valid_sources[0x72]	387	1		T1	5		T6	1		T8	1
valid_sources[0x73]	427	1		T16	1		T4	10		T13	3
valid_sources[0x74]	417	1		T2	2		T3	1		T6	1
valid_sources[0x75]	780	1		T2	1		T3	2		T6	1
valid_sources[0x76]	340	1		T1	1		T16	1		T4	5
valid_sources[0x77]	416	1		T2	1		T4	5		T13	7
valid_sources[0x78]	358	1		T3	1		T6	1		T4	7
valid_sources[0x79]	337	1		T6	2		T13	53		T45	4
valid_sources[0x7a]	571	1		T2	1		T3	3		T6	2
valid_sources[0x7b]	386	1		T2	2		T6	1		T16	1
valid_sources[0x7c]	418	1		T6	2		T4	10		T31	32
valid_sources[0x7d]	442	1		T16	1		T4	10		T13	21
valid_sources[0x7e]	439	1		T1	1		T2	1		T3	1
valid_sources[0x7f]	629	1		T1	2		T2	5		T6	3
valid_sources[0x80]	481	1		T1	1		T3	4		T6	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25234

1

T1

41

T2

40

T3

4

values[0x0]

all_enables

biggest_size

19011

1

T1

40

T2

43

T3

11

values[0x1]

all_enables

biggest_size

16791

1

T1

30

T2

62

T3

6