Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	76560	1		T1	56		T2	576		T3	97
full_word	62081	1		T1	111		T2	180		T3	21

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	138331	1		T1	167		T2	756		T3	118
auto[TlIntgErrCmd]	107	1		T4	1		T13	9		T26	6
auto[TlIntgErrData]	98	1		T4	5		T13	4		T26	5
auto[TlIntgErrBoth]	105	1		T4	4		T13	7		T26	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	77526	1		T1	82		T2	117		T3	92
auto[1]	61115	1		T1	85		T2	639		T3	26

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	51971	1		T1	41		T2	72		T3	88
auto[TlIntgErrNone]	partial	auto[1]	24308	1		T1	15		T2	504		T3	9
auto[TlIntgErrNone]	full_word	auto[0]	25412	1		T1	41		T2	45		T3	4
auto[TlIntgErrNone]	full_word	auto[1]	36640	1		T1	70		T2	135		T3	17
auto[TlIntgErrCmd]	partial	auto[0]	47	1		T4	1		T13	7		T26	5
auto[TlIntgErrCmd]	partial	auto[1]	50	1		T13	2		T26	1		T27	3
auto[TlIntgErrCmd]	full_word	auto[0]	9	1		T27	1		T30	1		T52	2
auto[TlIntgErrCmd]	full_word	auto[1]	1	1		T27	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	37	1		T4	2		T13	3		T26	3
auto[TlIntgErrData]	partial	auto[1]	54	1		T4	3		T13	1		T26	2
auto[TlIntgErrData]	full_word	auto[0]	4	1		T49	1		T75	1		T76	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T52	1		T53	1		T77	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1		T4	2		T13	3		T26	5
auto[TlIntgErrBoth]	partial	auto[1]	52	1		T4	2		T13	3		T26	4
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T27	1		T30	1		T78	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1		T13	1		T28	1		T79	1