Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
23.17	0.00	0.00	92.66		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1952719	12462	0	0
ep_in_enable_rd_A	1952719	3834	0	0
ep_out_enable_rd_A	1952719	3158	0	0
in_iso_rd_A	1952719	3573	0	0
intr_enable_rd_A	1952719	4436	0	0
out_iso_rd_A	1952719	3068	0	0
phy_config_rd_A	1952719	2217	0	0
phy_pins_drive_rd_A	1952719	2642	0	0
rxenable_setup_rd_A	1952719	3496	0	0
set_nak_out_rd_A	1952719	3272	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1952719	12462	0	0
T2	6130	282	0	0
T3	2428	0	0	0
T4	60205	0	0	0
T5	0	25	0	0
T6	12875	834	0	0
T7	1715	0	0	0
T8	2144	0	0	0
T9	58430	0	0	0
T13	0	4	0	0
T15	2661	0	0	0
T16	2986	0	0	0
T18	1882	0	0	0
T19	0	845	0	0
T20	0	579	0	0
T21	0	1050	0	0
T26	0	3	0	0
T27	0	4	0	0
T28	0	4	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1952719	3834	0	0
T4	60205	250	0	0
T5	4965	0	0	0
T9	58430	0	0	0
T13	27951	0	0	0
T17	1631	0	0	0
T18	1882	0	0	0
T30	0	554	0	0
T31	0	455	0	0
T35	0	16	0	0
T36	1759	0	0	0
T37	1883	0	0	0
T38	2602	0	0	0
T39	0	8	0	0
T45	8193	0	0	0
T46	0	17	0	0
T52	0	310	0	0
T53	0	495	0	0
T54	0	98	0	0
T55	0	49	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1952719	3158	0	0
T4	60205	180	0	0
T5	4965	0	0	0
T9	58430	0	0	0
T10	0	8	0	0
T13	27951	0	0	0
T17	1631	0	0	0
T18	1882	0	0	0
T30	0	400	0	0
T31	0	421	0	0
T35	0	5	0	0
T36	1759	0	0	0
T37	1883	0	0	0
T38	2602	0	0	0
T39	0	4	0	0
T45	8193	0	0	0
T46	0	6	0	0
T52	0	174	0	0
T53	0	442	0	0
T54	0	87	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1952719	3573	0	0
T4	60205	289	0	0
T5	4965	0	0	0
T9	58430	0	0	0
T13	27951	0	0	0
T17	1631	0	0	0
T18	1882	0	0	0
T30	0	436	0	0
T31	0	457	0	0
T35	0	11	0	0
T36	1759	0	0	0
T37	1883	0	0	0
T38	2602	0	0	0
T39	0	39	0	0
T45	8193	0	0	0
T46	0	2	0	0
T52	0	300	0	0
T53	0	499	0	0
T54	0	40	0	0
T55	0	37	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1952719	4436	0	0
T4	60205	698	0	0
T5	4965	0	0	0
T9	58430	0	0	0
T10	0	5	0	0
T13	27951	0	0	0
T17	1631	0	0	0
T18	1882	0	0	0
T30	0	485	0	0
T31	0	437	0	0
T35	0	2	0	0
T36	1759	2	0	0
T37	1883	0	0	0
T38	2602	0	0	0
T45	8193	0	0	0
T46	0	9	0	0
T56	0	17	0	0
T57	0	10	0	0
T58	0	25	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1952719	3068	0	0
T4	60205	224	0	0
T5	4965	0	0	0
T9	58430	0	0	0
T10	0	5	0	0
T13	27951	0	0	0
T17	1631	0	0	0
T18	1882	0	0	0
T30	0	428	0	0
T31	0	439	0	0
T35	0	24	0	0
T36	1759	0	0	0
T37	1883	0	0	0
T38	2602	0	0	0
T45	8193	0	0	0
T46	0	24	0	0
T52	0	255	0	0
T53	0	397	0	0
T54	0	75	0	0
T55	0	4	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1952719	2217	0	0
T4	60205	166	0	0
T5	4965	0	0	0
T9	58430	0	0	0
T13	27951	0	0	0
T17	1631	0	0	0
T18	1882	0	0	0
T30	0	205	0	0
T31	0	424	0	0
T35	0	11	0	0
T36	1759	0	0	0
T37	1883	0	0	0
T38	2602	0	0	0
T39	0	5	0	0
T45	8193	0	0	0
T46	0	7	0	0
T52	0	148	0	0
T53	0	290	0	0
T54	0	27	0	0
T55	0	21	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1952719	2642	0	0
T4	60205	164	0	0
T5	4965	0	0	0
T9	58430	0	0	0
T10	0	5	0	0
T13	27951	0	0	0
T17	1631	0	0	0
T18	1882	0	0	0
T30	0	372	0	0
T31	0	442	0	0
T35	0	6	0	0
T36	1759	0	0	0
T37	1883	0	0	0
T38	2602	0	0	0
T39	0	11	0	0
T45	8193	0	0	0
T46	0	12	0	0
T52	0	144	0	0
T53	0	397	0	0
T54	0	54	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1952719	3496	0	0
T4	60205	241	0	0
T5	4965	0	0	0
T9	58430	0	0	0
T10	0	1	0	0
T13	27951	0	0	0
T17	1631	0	0	0
T18	1882	0	0	0
T30	0	395	0	0
T31	0	439	0	0
T35	0	26	0	0
T36	1759	0	0	0
T37	1883	0	0	0
T38	2602	0	0	0
T39	0	2	0	0
T45	8193	0	0	0
T46	0	16	0	0
T52	0	367	0	0
T53	0	461	0	0
T54	0	120	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1952719	3272	0	0
T4	60205	165	0	0
T5	4965	0	0	0
T9	58430	0	0	0
T10	0	6	0	0
T13	27951	0	0	0
T17	1631	0	0	0
T18	1882	0	0	0
T30	0	508	0	0
T31	0	473	0	0
T35	0	16	0	0
T36	1759	0	0	0
T37	1883	0	0	0
T38	2602	0	0	0
T39	0	4	0	0
T45	8193	0	0	0
T46	0	9	0	0
T52	0	155	0	0
T53	0	489	0	0
T54	0	37	0	0