Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	60353	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	58522	1		T1	18		T2	418		T3	14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	74879	1		T1	11		T2	1922		T3	11
values[0x0]	21621	1		T1	7		T2	253		T3	7
values[0x1]	22375	1		T1	4		T2	258		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	41969	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	76906	1		T1	19		T2	1040		T3	16

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	456	1		T2	6		T6	23		T8	1
valid_sources[0x01]	398	1		T2	9		T16	8		T6	28
valid_sources[0x02]	294	1		T2	7		T16	8		T6	10
valid_sources[0x03]	466	1		T2	7		T16	5		T6	25
valid_sources[0x04]	443	1		T2	1		T16	1		T6	4
valid_sources[0x05]	337	1		T2	17		T4	3		T6	5
valid_sources[0x06]	493	1		T2	10		T16	11		T6	6
valid_sources[0x07]	316	1		T2	2		T4	3		T6	9
valid_sources[0x08]	621	1		T4	3		T16	13		T6	7
valid_sources[0x09]	360	1		T2	13		T6	19		T18	1
valid_sources[0x0a]	310	1		T2	3		T4	1		T6	17
valid_sources[0x0b]	471	1		T2	8		T16	4		T6	19
valid_sources[0x0c]	440	1		T2	4		T16	6		T6	1
valid_sources[0x0d]	294	1		T2	22		T4	2		T16	5
valid_sources[0x0e]	395	1		T2	17		T16	2		T6	4
valid_sources[0x0f]	730	1		T2	9		T16	3		T6	20
valid_sources[0x10]	511	1		T2	28		T4	1		T16	2
valid_sources[0x11]	427	1		T2	19		T4	2		T16	7
valid_sources[0x12]	341	1		T2	8		T6	13		T18	2
valid_sources[0x13]	363	1		T2	14		T6	15		T8	1
valid_sources[0x14]	473	1		T2	10		T4	1		T16	4
valid_sources[0x15]	344	1		T6	13		T8	3		T7	1
valid_sources[0x16]	492	1		T2	6		T4	2		T6	12
valid_sources[0x17]	442	1		T2	5		T3	4		T16	5
valid_sources[0x18]	382	1		T2	16		T4	2		T16	16
valid_sources[0x19]	591	1		T2	14		T4	2		T16	3
valid_sources[0x1a]	324	1		T2	11		T12	2		T6	4
valid_sources[0x1b]	660	1		T2	2		T6	8		T8	2
valid_sources[0x1c]	394	1		T2	1		T4	2		T6	5
valid_sources[0x1d]	403	1		T2	9		T6	8		T5	6
valid_sources[0x1e]	510	1		T16	2		T6	19		T5	5
valid_sources[0x1f]	444	1		T2	2		T16	2		T6	5
valid_sources[0x20]	717	1		T2	2		T4	1		T16	21
valid_sources[0x21]	477	1		T2	28		T16	1		T6	8
valid_sources[0x22]	427	1		T2	4		T16	15		T6	7
valid_sources[0x23]	401	1		T2	19		T4	4		T6	11
valid_sources[0x24]	629	1		T2	31		T16	8		T6	10
valid_sources[0x25]	616	1		T2	10		T4	3		T16	5
valid_sources[0x26]	365	1		T2	17		T16	1		T6	6
valid_sources[0x27]	497	1		T2	18		T16	3		T6	7
valid_sources[0x28]	400	1		T3	3		T16	1		T6	4
valid_sources[0x29]	609	1		T6	5		T5	61		T7	11
valid_sources[0x2a]	506	1		T2	12		T16	1		T6	12
valid_sources[0x2b]	361	1		T2	2		T6	7		T8	3
valid_sources[0x2c]	404	1		T2	53		T4	2		T16	2
valid_sources[0x2d]	423	1		T2	4		T12	3		T6	8
valid_sources[0x2e]	813	1		T2	4		T4	1		T16	1
valid_sources[0x2f]	409	1		T2	25		T16	6		T6	11
valid_sources[0x30]	593	1		T2	8		T4	1		T6	6
valid_sources[0x31]	559	1		T2	7		T4	1		T6	14
valid_sources[0x32]	425	1		T2	15		T6	5		T8	2
valid_sources[0x33]	328	1		T2	1		T4	1		T16	1
valid_sources[0x34]	505	1		T2	9		T6	4		T8	2
valid_sources[0x35]	506	1		T16	3		T6	5		T8	3
valid_sources[0x36]	459	1		T2	12		T6	30		T5	6
valid_sources[0x37]	353	1		T2	1		T12	6		T16	13
valid_sources[0x38]	623	1		T2	3		T4	3		T16	2
valid_sources[0x39]	458	1		T2	18		T4	3		T6	18
valid_sources[0x3a]	425	1		T2	5		T4	1		T16	3
valid_sources[0x3b]	308	1		T6	21		T8	2		T5	1
valid_sources[0x3c]	523	1		T2	9		T16	10		T6	7
valid_sources[0x3d]	713	1		T2	30		T6	24		T7	5
valid_sources[0x3e]	312	1		T2	11		T6	12		T5	8
valid_sources[0x3f]	528	1		T2	11		T4	4		T6	9
valid_sources[0x40]	590	1		T2	26		T6	18		T8	5
valid_sources[0x41]	348	1		T2	5		T4	3		T6	6
valid_sources[0x42]	532	1		T2	29		T4	1		T6	6
valid_sources[0x43]	430	1		T2	9		T16	3		T6	11
valid_sources[0x44]	354	1		T2	4		T4	6		T16	2
valid_sources[0x45]	327	1		T2	3		T4	4		T12	1
valid_sources[0x46]	536	1		T2	15		T4	2		T16	3
valid_sources[0x47]	629	1		T2	20		T4	1		T6	10
valid_sources[0x48]	336	1		T2	29		T6	9		T19	3
valid_sources[0x49]	685	1		T2	10		T3	4		T16	17
valid_sources[0x4a]	415	1		T2	5		T6	19		T8	2
valid_sources[0x4b]	367	1		T2	1		T16	5		T6	18
valid_sources[0x4c]	379	1		T2	14		T16	1		T6	7
valid_sources[0x4d]	389	1		T2	14		T4	4		T16	14
valid_sources[0x4e]	490	1		T2	18		T6	19		T8	4
valid_sources[0x4f]	410	1		T2	16		T4	1		T6	18
valid_sources[0x50]	513	1		T2	1		T4	1		T6	12
valid_sources[0x51]	477	1		T16	3		T8	2		T18	4
valid_sources[0x52]	391	1		T2	9		T4	1		T6	5
valid_sources[0x53]	495	1		T2	11		T12	2		T16	2
valid_sources[0x54]	527	1		T2	19		T4	1		T16	1
valid_sources[0x55]	467	1		T2	1		T4	1		T16	2
valid_sources[0x56]	313	1		T2	3		T16	10		T6	7
valid_sources[0x57]	555	1		T2	1		T16	17		T6	14
valid_sources[0x58]	452	1		T2	4		T4	2		T16	9
valid_sources[0x59]	421	1		T2	4		T16	2		T6	9
valid_sources[0x5a]	311	1		T2	18		T4	2		T16	7
valid_sources[0x5b]	380	1		T2	7		T6	13		T18	2
valid_sources[0x5c]	482	1		T2	12		T4	1		T6	12
valid_sources[0x5d]	378	1		T2	14		T6	27		T8	1
valid_sources[0x5e]	414	1		T2	2		T4	1		T16	5
valid_sources[0x5f]	688	1		T2	7		T16	3		T6	13
valid_sources[0x60]	423	1		T2	23		T6	9		T8	4
valid_sources[0x61]	368	1		T16	8		T6	29		T8	2
valid_sources[0x62]	399	1		T2	2		T16	4		T6	5
valid_sources[0x63]	533	1		T2	14		T6	17		T18	5
valid_sources[0x64]	661	1		T2	21		T4	1		T16	10
valid_sources[0x65]	316	1		T2	2		T6	21		T8	3
valid_sources[0x66]	455	1		T2	24		T4	3		T16	2
valid_sources[0x67]	287	1		T2	10		T16	12		T6	10
valid_sources[0x68]	464	1		T2	10		T16	2		T6	2
valid_sources[0x69]	420	1		T2	12		T4	2		T16	3
valid_sources[0x6a]	316	1		T2	11		T16	3		T6	4
valid_sources[0x6b]	310	1		T2	10		T16	4		T6	24
valid_sources[0x6c]	406	1		T2	18		T6	3		T8	1
valid_sources[0x6d]	457	1		T2	10		T6	14		T8	2
valid_sources[0x6e]	516	1		T2	28		T16	12		T6	19
valid_sources[0x6f]	327	1		T6	14		T18	1		T19	1
valid_sources[0x70]	568	1		T4	3		T6	12		T8	3
valid_sources[0x71]	521	1		T2	9		T6	7		T8	6
valid_sources[0x72]	566	1		T2	10		T16	2		T6	8
valid_sources[0x73]	491	1		T2	22		T6	5		T8	1
valid_sources[0x74]	569	1		T2	9		T6	7		T8	1
valid_sources[0x75]	337	1		T2	9		T16	2		T6	5
valid_sources[0x76]	525	1		T6	47		T8	3		T5	11
valid_sources[0x77]	553	1		T2	8		T4	2		T16	5
valid_sources[0x78]	380	1		T2	3		T16	6		T6	10
valid_sources[0x79]	549	1		T2	20		T16	4		T6	20
valid_sources[0x7a]	578	1		T2	8		T4	1		T6	1
valid_sources[0x7b]	741	1		T2	8		T16	3		T6	10
valid_sources[0x7c]	451	1		T2	6		T16	7		T6	1
valid_sources[0x7d]	328	1		T2	1		T16	4		T6	13
valid_sources[0x7e]	569	1		T2	12		T16	12		T6	11
valid_sources[0x7f]	566	1		T2	20		T16	1		T6	20
valid_sources[0x80]	353	1		T2	15		T4	2		T16	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

23808

1

T1

8

T2

117

T3

4

values[0x0]

all_enables

biggest_size

18404

1

T1

7

T2

167

T3

7

values[0x1]

all_enables

biggest_size

16310

1

T1

3

T2

134

T3

3