Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	74285	1		T1	4		T2	2022		T3	8
full_word	59490	1		T1	18		T2	418		T3	14

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	133445	1		T1	22		T2	2420		T3	22
auto[TlIntgErrCmd]	109	1		T2	6		T5	4		T28	5
auto[TlIntgErrData]	109	1		T2	5		T5	11		T28	3
auto[TlIntgErrBoth]	112	1		T2	9		T5	5		T28	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	76730	1		T1	11		T2	1926		T3	11
auto[1]	57045	1		T1	11		T2	514		T3	11

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	52582	1		T1	3		T2	1803		T3	7
auto[TlIntgErrNone]	partial	auto[1]	21400	1		T1	1		T2	201		T3	1
auto[TlIntgErrNone]	full_word	auto[0]	23991	1		T1	8		T2	116		T3	4
auto[TlIntgErrNone]	full_word	auto[1]	35472	1		T1	10		T2	300		T3	10
auto[TlIntgErrCmd]	partial	auto[0]	38	1		T2	1		T5	2		T28	1
auto[TlIntgErrCmd]	partial	auto[1]	58	1		T2	4		T5	1		T28	3
auto[TlIntgErrCmd]	full_word	auto[0]	6	1		T2	1		T5	1		T28	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1		T26	1		T59	2		T75	1
auto[TlIntgErrData]	partial	auto[0]	57	1		T2	1		T5	5		T28	1
auto[TlIntgErrData]	partial	auto[1]	44	1		T2	3		T5	5		T28	2
auto[TlIntgErrData]	full_word	auto[0]	1	1		T5	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	7	1		T2	1		T59	1		T75	1
auto[TlIntgErrBoth]	partial	auto[0]	54	1		T2	4		T5	1		T28	1
auto[TlIntgErrBoth]	partial	auto[1]	52	1		T2	5		T5	2		T28	1
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T5	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T5	1		T77	1		T51	2