Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 74285 1 T1 4 T2 2022 T3 8
full_word 59490 1 T1 18 T2 418 T3 14



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 133445 1 T1 22 T2 2420 T3 22
auto[TlIntgErrCmd] 109 1 T2 6 T5 4 T28 5
auto[TlIntgErrData] 109 1 T2 5 T5 11 T28 3
auto[TlIntgErrBoth] 112 1 T2 9 T5 5 T28 2



Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 76730 1 T1 11 T2 1926 T3 11
auto[1] 57045 1 T1 11 T2 514 T3 11



Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 52582 1 T1 3 T2 1803 T3 7
auto[TlIntgErrNone] partial auto[1] 21400 1 T1 1 T2 201 T3 1
auto[TlIntgErrNone] full_word auto[0] 23991 1 T1 8 T2 116 T3 4
auto[TlIntgErrNone] full_word auto[1] 35472 1 T1 10 T2 300 T3 10
auto[TlIntgErrCmd] partial auto[0] 38 1 T2 1 T5 2 T28 1
auto[TlIntgErrCmd] partial auto[1] 58 1 T2 4 T5 1 T28 3
auto[TlIntgErrCmd] full_word auto[0] 6 1 T2 1 T5 1 T28 1
auto[TlIntgErrCmd] full_word auto[1] 7 1 T26 1 T59 2 T75 1
auto[TlIntgErrData] partial auto[0] 57 1 T2 1 T5 5 T28 1
auto[TlIntgErrData] partial auto[1] 44 1 T2 3 T5 5 T28 2
auto[TlIntgErrData] full_word auto[0] 1 1 T5 1 - - - -
auto[TlIntgErrData] full_word auto[1] 7 1 T2 1 T59 1 T75 1
auto[TlIntgErrBoth] partial auto[0] 54 1 T2 4 T5 1 T28 1
auto[TlIntgErrBoth] partial auto[1] 52 1 T2 5 T5 2 T28 1
auto[TlIntgErrBoth] full_word auto[0] 1 1 T5 1 - - - -
auto[TlIntgErrBoth] full_word auto[1] 5 1 T5 1 T77 1 T51 2

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