Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
23.39	0.00	0.00	93.58		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1768337	10751	0	0
ep_in_enable_rd_A	1768337	2417	0	0
ep_out_enable_rd_A	1768337	2266	0	0
in_iso_rd_A	1768337	2548	0	0
intr_enable_rd_A	1768337	3256	0	0
out_iso_rd_A	1768337	2097	0	0
phy_config_rd_A	1768337	1753	0	0
phy_pins_drive_rd_A	1768337	2085	0	0
rxenable_setup_rd_A	1768337	2076	0	0
set_nak_out_rd_A	1768337	2879	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1768337	10751	0	0
T2	31196	6	0	0
T3	2025	0	0	0
T4	5516	0	0	0
T5	82978	6	0	0
T6	23345	0	0	0
T7	4204	6	0	0
T8	7283	0	0	0
T12	1640	0	0	0
T16	9973	0	0	0
T17	2813	0	0	0
T18	0	851	0	0
T19	0	21	0	0
T20	0	17	0	0
T21	0	8	0	0
T22	0	582	0	0
T26	0	6	0	0
T28	0	2	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1768337	2417	0	0
T4	5516	5	0	0
T5	82978	0	0	0
T6	23345	0	0	0
T7	4204	0	0	0
T8	7283	0	0	0
T12	1640	0	0	0
T13	3347	0	0	0
T16	9973	0	0	0
T17	2813	0	0	0
T18	5317	0	0	0
T19	0	7	0	0
T28	0	182	0	0
T34	0	7	0	0
T40	0	12	0	0
T41	0	3	0	0
T57	0	23	0	0
T59	0	652	0	0
T60	0	29	0	0
T61	0	40	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1768337	2266	0	0
T4	5516	2	0	0
T5	82978	0	0	0
T6	23345	0	0	0
T7	4204	0	0	0
T8	7283	8	0	0
T9	0	5	0	0
T12	1640	0	0	0
T13	3347	0	0	0
T16	9973	0	0	0
T17	2813	0	0	0
T18	5317	0	0	0
T19	0	29	0	0
T27	0	2	0	0
T28	0	96	0	0
T34	0	8	0	0
T40	0	5	0	0
T41	0	46	0	0
T59	0	427	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1768337	2548	0	0
T4	5516	10	0	0
T5	82978	0	0	0
T6	23345	0	0	0
T7	4204	0	0	0
T8	7283	33	0	0
T12	1640	0	0	0
T13	3347	0	0	0
T16	9973	0	0	0
T17	2813	0	0	0
T18	5317	0	0	0
T19	0	12	0	0
T28	0	261	0	0
T34	0	5	0	0
T40	0	22	0	0
T41	0	45	0	0
T57	0	21	0	0
T59	0	493	0	0
T60	0	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1768337	3256	0	0
T4	5516	2	0	0
T5	82978	0	0	0
T6	23345	0	0	0
T7	4204	0	0	0
T8	7283	15	0	0
T9	0	3	0	0
T12	1640	0	0	0
T13	3347	15	0	0
T16	9973	0	0	0
T17	2813	0	0	0
T18	5317	0	0	0
T19	0	82	0	0
T27	0	10	0	0
T28	0	296	0	0
T34	0	55	0	0
T40	0	5	0	0
T41	0	78	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1768337	2097	0	0
T4	5516	4	0	0
T5	82978	0	0	0
T6	23345	0	0	0
T7	4204	0	0	0
T8	7283	33	0	0
T9	0	5	0	0
T12	1640	0	0	0
T13	3347	0	0	0
T16	9973	0	0	0
T17	2813	0	0	0
T18	5317	0	0	0
T19	0	53	0	0
T28	0	132	0	0
T34	0	7	0	0
T40	0	3	0	0
T41	0	44	0	0
T53	0	6	0	0
T59	0	408	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1768337	1753	0	0
T4	5516	7	0	0
T5	82978	0	0	0
T6	23345	0	0	0
T7	4204	0	0	0
T8	7283	14	0	0
T9	0	9	0	0
T12	1640	0	0	0
T13	3347	0	0	0
T16	9973	0	0	0
T17	2813	0	0	0
T18	5317	0	0	0
T19	0	24	0	0
T27	0	8	0	0
T28	0	149	0	0
T34	0	10	0	0
T40	0	15	0	0
T41	0	33	0	0
T59	0	248	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1768337	2085	0	0
T4	5516	6	0	0
T5	82978	0	0	0
T6	23345	0	0	0
T7	4204	0	0	0
T8	7283	10	0	0
T9	0	1	0	0
T12	1640	0	0	0
T13	3347	0	0	0
T16	9973	0	0	0
T17	2813	0	0	0
T18	5317	0	0	0
T19	0	44	0	0
T28	0	126	0	0
T34	0	40	0	0
T40	0	11	0	0
T41	0	4	0	0
T57	0	14	0	0
T59	0	377	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1768337	2076	0	0
T4	5516	7	0	0
T5	82978	0	0	0
T6	23345	0	0	0
T7	4204	0	0	0
T8	7283	30	0	0
T12	1640	0	0	0
T13	3347	0	0	0
T16	9973	0	0	0
T17	2813	0	0	0
T18	5317	0	0	0
T19	0	34	0	0
T28	0	115	0	0
T34	0	33	0	0
T40	0	17	0	0
T41	0	8	0	0
T57	0	53	0	0
T59	0	269	0	0
T60	0	70	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1768337	2879	0	0
T4	5516	5	0	0
T5	82978	0	0	0
T6	23345	0	0	0
T7	4204	0	0	0
T8	7283	5	0	0
T9	0	4	0	0
T12	1640	0	0	0
T13	3347	0	0	0
T16	9973	0	0	0
T17	2813	0	0	0
T18	5317	0	0	0
T19	0	12	0	0
T28	0	208	0	0
T34	0	5	0	0
T40	0	23	0	0
T41	0	37	0	0
T57	0	75	0	0
T59	0	668	0	0