Module Definition
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Module : prim_sync_reqack
SCORELINECONDTOGGLEFSMBRANCHASSERT
58.33 83.33 33.33 66.67 50.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_wake_events_cdc.u_arb.gen_wr_req.u_dst_update_sync 58.33 83.33 33.33 66.67 50.00



Module Instance : tb.dut.u_reg.u_wake_events_cdc.u_arb.gen_wr_req.u_dst_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
58.33 83.33 33.33 66.67 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
62.71 87.50 33.33 80.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
46.50 76.00 53.49 56.52 0.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_sync_reqack
Line No.TotalCoveredPercent
TOTAL363083.33
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS21912758.33
ALWAYS263121191.67
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 0 1
MISSING_ELSE
241 0 1
242 0 1
245 0 1
246 0 1
==> MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 0 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Module : prim_sync_reqack
TotalCoveredPercent
Conditions6233.33
Logical6233.33
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT4,T9,T10
11Not Covered

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT10

Branch Coverage for Module : prim_sync_reqack
Line No.TotalCoveredPercent
Branches 12 8 66.67
CASE 225 4 1 25.00
CASE 269 4 3 75.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Not Covered
EVEN 0 - Covered T4,T9,T10
ODD - 1 Not Covered
ODD - 0 Not Covered


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T10
EVEN 0 - Covered T1,T2,T3
ODD - 1 Not Covered
ODD - 0 Covered T10


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_sync_reqack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 1768337 1 0 0
SyncReqAckHoldReq 20105 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 1768337 1 0 0
T10 4544 1 0 0
T24 4942 0 0 0
T27 15023 0 0 0
T33 7625 0 0 0
T41 2454 0 0 0
T44 9290 0 0 0
T45 4970 0 0 0
T46 2485 0 0 0
T47 3847 0 0 0
T48 9453 0 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 20105 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%