SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
0.00 | 0.00 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
0.00 | 0.00 | 0.00 | 0.00 | 0.00 | u_usb_fs_tx |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_generic.u_impl_generic | 0.00 | 0.00 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
0.00 | 0.00 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
0.00 | 0.00 | 0.00 | 0.00 | 0.00 | u_usb_fs_tx |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_generic.u_impl_generic | 0.00 | 0.00 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
0.00 | 0.00 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
0.00 | 0.00 | 0.00 | 0.00 | 0.00 | u_usb_fs_tx |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_generic.u_impl_generic | 0.00 | 0.00 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
0.00 | 0.00 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
0.00 | 0.00 | 0.00 | 0.00 | 0.00 | u_usb_fs_tx |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_generic.u_impl_generic | 0.00 | 0.00 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
0.00 | 0.00 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
0.00 | 0.00 | 0.00 | 0.00 | 0.00 | u_usb_fs_tx |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_generic.u_impl_generic | 0.00 | 0.00 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
0.00 | 0.00 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
0.00 | 0.00 | 0.00 | 0.00 | 0.00 | u_usb_fs_tx |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_generic.u_impl_generic | 0.00 | 0.00 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
0.00 | 0.00 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
0.00 | 0.00 | 0.00 | 0.00 | 0.00 | u_usb_fs_tx |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_generic.u_impl_generic | 0.00 | 0.00 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
prim_flop_2sync |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
prim_flop_2sync |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
prim_flop_2sync |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
prim_flop_2sync |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
prim_flop_2sync |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
prim_flop_2sync |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_nrz_hs_protocol.req_sync |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_nrz_hs_protocol.req_sync |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_nrz_hs_protocol.ack_sync |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_nrz_hs_protocol.ack_sync |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.31 | 99.76 | 97.48 | 100.00 | 100.00 | u_reg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.31 | 99.76 | 97.48 | 100.00 | 100.00 | u_reg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
0.00 | 0.00 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
cdc_io_to_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_generic.u_impl_generic | 0.00 | 0.00 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
0.00 | 0.00 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
cdc_io_to_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_generic.u_impl_generic | 0.00 | 0.00 | 0.00 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |