Unified Coverage Report :: Module :: prim_pulse_sync

Module : prim_pulse_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_wake_events_cdc.u_src_to_dst_req	54.76	85.71	33.33			100.00	0.00
tb.dut.u_reg.u_wake_control_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_wake_control_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wake_events_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
54.76	85.71	33.33			100.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
56.41	92.31	33.33			100.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
68.40	94.12	46.15			83.33	50.00	u_wake_events_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_wake_control_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_wake_control_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_wake_control_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	33.33	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1143152075	2450	0	0
SrcPulseCheck_M	2147483647	2474	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143152075	2450	0	0
T6	678209	4	0	0
T7	0	4	0	0
T8	0	4	0	0
T9	0	4	0	0
T10	0	4	0	0
T11	0	4	0	0
T12	0	4	0	0
T13	0	4	0	0
T14	0	4	0	0
T15	0	4	0	0
T16	491889	0	0	0
T17	491202	0	0	0
T18	487909	0	0	0
T19	537657	0	0	0
T20	495929	0	0	0
T21	488473	0	0	0
T22	490205	0	0	0
T23	487206	0	0	0
T24	486824	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2474	0	0
T6	678209	4	0	0
T7	0	4	0	0
T8	0	4	0	0
T9	0	4	0	0
T10	0	4	0	0
T11	0	4	0	0
T12	0	4	0	0
T13	0	4	0	0
T14	0	4	0	0
T15	0	4	0	0
T16	491889	0	0	0
T17	491202	0	0	0
T18	487909	0	0	0
T19	537657	0	0	0
T20	495929	0	0	0
T21	488473	0	0	0
T22	490205	0	0	0
T23	487206	0	0	0
T24	486824	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	0	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	6	2	33.33
Logical	6	2	33.33
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	0	0.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	0	0.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	13435146	0	0	0
SrcPulseCheck_M	1116281783	0	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13435146	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1116281783	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Branch Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	13435146	1219	0	0
SrcPulseCheck_M	1116281783	1243	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13435146	1219	0	0
T6	6354	2	0	0
T7	0	2	0	0
T8	0	2	0	0
T9	0	2	0	0
T10	0	2	0	0
T11	0	2	0	0
T12	0	2	0	0
T13	0	2	0	0
T14	0	2	0	0
T15	0	2	0	0
T16	8459	0	0	0
T17	7050	0	0	0
T18	5109	0	0	0
T19	8521	0	0	0
T20	9247	0	0	0
T21	5225	0	0	0
T22	7343	0	0	0
T23	4535	0	0	0
T24	3493	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1116281783	1243	0	0
T6	671855	2	0	0
T7	0	2	0	0
T8	0	2	0	0
T9	0	2	0	0
T10	0	2	0	0
T11	0	2	0	0
T12	0	2	0	0
T13	0	2	0	0
T14	0	2	0	0
T15	0	2	0	0
T16	483430	0	0	0
T17	484152	0	0	0
T18	482800	0	0	0
T19	529136	0	0	0
T20	486682	0	0	0
T21	483248	0	0	0
T22	482862	0	0	0
T23	482671	0	0	0
T24	483331	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Branch Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1116281783	1231	0	0
SrcPulseCheck_M	13435146	1231	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1116281783	1231	0	0
T6	671855	2	0	0
T7	0	2	0	0
T8	0	2	0	0
T9	0	2	0	0
T10	0	2	0	0
T11	0	2	0	0
T12	0	2	0	0
T13	0	2	0	0
T14	0	2	0	0
T15	0	2	0	0
T16	483430	0	0	0
T17	484152	0	0	0
T18	482800	0	0	0
T19	529136	0	0	0
T20	486682	0	0	0
T21	483248	0	0	0
T22	482862	0	0	0
T23	482671	0	0	0
T24	483331	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	13435146	1231	0	0
T6	6354	2	0	0
T7	0	2	0	0
T8	0	2	0	0
T9	0	2	0	0
T10	0	2	0	0
T11	0	2	0	0
T12	0	2	0	0
T13	0	2	0	0
T14	0	2	0	0
T15	0	2	0	0
T16	8459	0	0	0
T17	7050	0	0	0
T18	5109	0	0	0
T19	8521	0	0	0
T20	9247	0	0	0
T21	5225	0	0	0
T22	7343	0	0	0
T23	4535	0	0	0
T24	3493	0	0	0