Line Coverage for Module :
prim_reg_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Module :
prim_reg_cdc
| Total | Covered | Percent |
Conditions | 14 | 12 | 85.71 |
Logical | 14 | 12 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T6,T7,T8 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T6,T7,T8 |
1 | 1 | Covered | T6,T7,T8 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T6,T7,T8 |
1 | 0 | Covered | T6,T7,T8 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T6,T7,T8 |
1 | 1 | Covered | T6,T7,T8 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T6,T7,T8 |
Branch Coverage for Module :
prim_reg_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T6,T7,T8 |
0 |
0 |
1 |
Covered |
T6,T7,T8 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T6,T7,T8 |
0 |
0 |
1 |
Covered |
T6,T7,T8 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_reg_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
397789 |
0 |
0 |
T6 |
671855 |
589 |
0 |
0 |
T7 |
0 |
291 |
0 |
0 |
T8 |
0 |
285 |
0 |
0 |
T9 |
0 |
767 |
0 |
0 |
T10 |
0 |
279 |
0 |
0 |
T11 |
0 |
524 |
0 |
0 |
T12 |
0 |
378 |
0 |
0 |
T13 |
0 |
491 |
0 |
0 |
T14 |
0 |
381 |
0 |
0 |
T15 |
0 |
531 |
0 |
0 |
T16 |
483430 |
0 |
0 |
0 |
T17 |
484152 |
0 |
0 |
0 |
T18 |
482800 |
0 |
0 |
0 |
T19 |
529136 |
0 |
0 |
0 |
T20 |
486682 |
0 |
0 |
0 |
T21 |
483248 |
0 |
0 |
0 |
T22 |
482862 |
0 |
0 |
0 |
T23 |
482671 |
0 |
0 |
0 |
T24 |
483331 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
26870292 |
26830232 |
0 |
0 |
T1 |
6922 |
6912 |
0 |
0 |
T2 |
13436 |
13418 |
0 |
0 |
T3 |
5638 |
5620 |
0 |
0 |
T4 |
46628 |
46616 |
0 |
0 |
T28 |
14684 |
14674 |
0 |
0 |
T29 |
16204 |
16188 |
0 |
0 |
T30 |
19814 |
19796 |
0 |
0 |
T31 |
19830 |
19812 |
0 |
0 |
T32 |
11262 |
11248 |
0 |
0 |
T33 |
11152 |
11132 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1231 |
0 |
0 |
T6 |
671855 |
2 |
0 |
0 |
T7 |
0 |
2 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
2 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
2 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
T16 |
483430 |
0 |
0 |
0 |
T17 |
484152 |
0 |
0 |
0 |
T18 |
482800 |
0 |
0 |
0 |
T19 |
529136 |
0 |
0 |
0 |
T20 |
486682 |
0 |
0 |
0 |
T21 |
483248 |
0 |
0 |
0 |
T22 |
482862 |
0 |
0 |
0 |
T23 |
482671 |
0 |
0 |
0 |
T24 |
483331 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
965928 |
965760 |
0 |
0 |
T2 |
971238 |
971118 |
0 |
0 |
T3 |
1546652 |
1546552 |
0 |
0 |
T4 |
482374 |
482362 |
0 |
0 |
T28 |
968198 |
968044 |
0 |
0 |
T29 |
967480 |
967340 |
0 |
0 |
T30 |
968550 |
968388 |
0 |
0 |
T31 |
963514 |
963324 |
0 |
0 |
T32 |
967286 |
967160 |
0 |
0 |
T33 |
969800 |
969608 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 17 | 16 | 94.12 |
CONT_ASSIGN | 65 | 0 | 0 | |
ALWAYS | 71 | 5 | 4 | 80.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 7 | 7 | 100.00 |
CONT_ASSIGN | 150 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
|
unreachable |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
|
unreachable |
75 |
1 |
1 |
76 |
0 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
|
unreachable |
124 |
|
unreachable |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
|
unreachable |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
| Total | Covered | Percent |
Conditions | 13 | 6 | 46.15 |
Logical | 13 | 6 | 46.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T6,T7,T8 |
1 | 0 | Not Covered | |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T6,T7,T8 |
Branch Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
5 |
83.33 |
IF |
71 |
3 |
2 |
66.67 |
IF |
115 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Unreachable |
|
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Unreachable |
|
0 |
0 |
1 |
Covered |
T6,T7,T8 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1116281783 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
13435146 |
13415116 |
0 |
0 |
T1 |
3461 |
3456 |
0 |
0 |
T2 |
6718 |
6709 |
0 |
0 |
T3 |
2819 |
2810 |
0 |
0 |
T4 |
23314 |
23308 |
0 |
0 |
T28 |
7342 |
7337 |
0 |
0 |
T29 |
8102 |
8094 |
0 |
0 |
T30 |
9907 |
9898 |
0 |
0 |
T31 |
9915 |
9906 |
0 |
0 |
T32 |
5631 |
5624 |
0 |
0 |
T33 |
5576 |
5566 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1116281783 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1116281783 |
1116073861 |
0 |
0 |
T1 |
482964 |
482880 |
0 |
0 |
T2 |
485619 |
485559 |
0 |
0 |
T3 |
773326 |
773276 |
0 |
0 |
T4 |
241187 |
241181 |
0 |
0 |
T28 |
484099 |
484022 |
0 |
0 |
T29 |
483740 |
483670 |
0 |
0 |
T30 |
484275 |
484194 |
0 |
0 |
T31 |
481757 |
481662 |
0 |
0 |
T32 |
483643 |
483580 |
0 |
0 |
T33 |
484900 |
484804 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T6,T7,T8 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T6,T7,T8 |
1 | 1 | Covered | T6,T7,T8 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T6,T7,T8 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T6,T7,T8 |
1 | 1 | Covered | T6,T7,T8 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T6,T7,T8 |
0 |
0 |
1 |
Covered |
T6,T7,T8 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T6,T7,T8 |
0 |
0 |
1 |
Covered |
T6,T7,T8 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1116281783 |
397789 |
0 |
0 |
T6 |
671855 |
589 |
0 |
0 |
T7 |
0 |
291 |
0 |
0 |
T8 |
0 |
285 |
0 |
0 |
T9 |
0 |
767 |
0 |
0 |
T10 |
0 |
279 |
0 |
0 |
T11 |
0 |
524 |
0 |
0 |
T12 |
0 |
378 |
0 |
0 |
T13 |
0 |
491 |
0 |
0 |
T14 |
0 |
381 |
0 |
0 |
T15 |
0 |
531 |
0 |
0 |
T16 |
483430 |
0 |
0 |
0 |
T17 |
484152 |
0 |
0 |
0 |
T18 |
482800 |
0 |
0 |
0 |
T19 |
529136 |
0 |
0 |
0 |
T20 |
486682 |
0 |
0 |
0 |
T21 |
483248 |
0 |
0 |
0 |
T22 |
482862 |
0 |
0 |
0 |
T23 |
482671 |
0 |
0 |
0 |
T24 |
483331 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
13435146 |
13415116 |
0 |
0 |
T1 |
3461 |
3456 |
0 |
0 |
T2 |
6718 |
6709 |
0 |
0 |
T3 |
2819 |
2810 |
0 |
0 |
T4 |
23314 |
23308 |
0 |
0 |
T28 |
7342 |
7337 |
0 |
0 |
T29 |
8102 |
8094 |
0 |
0 |
T30 |
9907 |
9898 |
0 |
0 |
T31 |
9915 |
9906 |
0 |
0 |
T32 |
5631 |
5624 |
0 |
0 |
T33 |
5576 |
5566 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1116281783 |
1231 |
0 |
0 |
T6 |
671855 |
2 |
0 |
0 |
T7 |
0 |
2 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
2 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
2 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
T16 |
483430 |
0 |
0 |
0 |
T17 |
484152 |
0 |
0 |
0 |
T18 |
482800 |
0 |
0 |
0 |
T19 |
529136 |
0 |
0 |
0 |
T20 |
486682 |
0 |
0 |
0 |
T21 |
483248 |
0 |
0 |
0 |
T22 |
482862 |
0 |
0 |
0 |
T23 |
482671 |
0 |
0 |
0 |
T24 |
483331 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1116281783 |
1116073861 |
0 |
0 |
T1 |
482964 |
482880 |
0 |
0 |
T2 |
485619 |
485559 |
0 |
0 |
T3 |
773326 |
773276 |
0 |
0 |
T4 |
241187 |
241181 |
0 |
0 |
T28 |
484099 |
484022 |
0 |
0 |
T29 |
483740 |
483670 |
0 |
0 |
T30 |
484275 |
484194 |
0 |
0 |
T31 |
481757 |
481662 |
0 |
0 |
T32 |
483643 |
483580 |
0 |
0 |
T33 |
484900 |
484804 |
0 |
0 |