Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8990035	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	9342206	1		T1	12		T2	4		T3	5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	17959076	1		T1	9		T2	4		T3	2
values[0x0]	185673	1		T1	4		T2	5		T3	6
values[0x1]	187492	1		T1	4		T2	2		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7174108	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	11158133	1		T1	13		T2	6		T3	7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52230	1		T95	2		T96	2		T5	1855
valid_sources[0x01]	51992	1		T95	2		T35	1		T4	21
valid_sources[0x02]	53467	1		T29	1		T95	4		T96	1
valid_sources[0x03]	52967	1		T95	4		T96	2		T5	1910
valid_sources[0x04]	52080	1		T95	4		T5	2007		T39	12
valid_sources[0x05]	52648	1		T30	1		T95	2		T5	1851
valid_sources[0x06]	52823	1		T95	1		T96	2		T5	1869
valid_sources[0x07]	53580	1		T95	6		T96	1		T5	1975
valid_sources[0x08]	99267	1		T95	2		T96	7		T5	1971
valid_sources[0x09]	52285	1		T95	7		T96	2		T5	1874
valid_sources[0x0a]	51995	1		T95	3		T96	3		T5	2010
valid_sources[0x0b]	53102	1		T1	1		T95	1		T5	1882
valid_sources[0x0c]	51806	1		T95	4		T5	1925		T39	50
valid_sources[0x0d]	53909	1		T34	1		T95	2		T96	3
valid_sources[0x0e]	85919	1		T31	1		T95	4		T96	1
valid_sources[0x0f]	52225	1		T95	3		T96	1		T5	1865
valid_sources[0x10]	157362	1		T95	5		T96	4		T5	1920
valid_sources[0x11]	52869	1		T95	2		T5	1928		T39	27
valid_sources[0x12]	51732	1		T95	1		T5	1908		T38	1
valid_sources[0x13]	51928	1		T95	3		T96	1		T5	1882
valid_sources[0x14]	51691	1		T95	2		T96	1		T5	1851
valid_sources[0x15]	52123	1		T95	3		T96	3		T5	1997
valid_sources[0x16]	52339	1		T29	3		T95	1		T96	2
valid_sources[0x17]	385412	1		T95	9		T96	2		T5	1905
valid_sources[0x18]	69568	1		T95	4		T96	7		T5	1847
valid_sources[0x19]	52275	1		T1	1		T95	4		T5	1776
valid_sources[0x1a]	52933	1		T95	2		T96	2		T99	1
valid_sources[0x1b]	52232	1		T95	2		T5	1897		T39	39
valid_sources[0x1c]	52278	1		T96	3		T5	1876		T39	23
valid_sources[0x1d]	52679	1		T95	3		T96	3		T5	1948
valid_sources[0x1e]	52178	1		T95	4		T5	1697		T39	29
valid_sources[0x1f]	52959	1		T95	2		T5	1930		T39	15
valid_sources[0x20]	53119	1		T95	2		T96	2		T5	1819
valid_sources[0x21]	51752	1		T95	5		T96	1		T5	1940
valid_sources[0x22]	52857	1		T95	1		T96	5		T5	1821
valid_sources[0x23]	54828	1		T95	2		T96	3		T5	1823
valid_sources[0x24]	54296	1		T95	5		T5	1824		T39	22
valid_sources[0x25]	52757	1		T95	4		T96	2		T93	1
valid_sources[0x26]	51799	1		T3	1		T95	2		T43	2
valid_sources[0x27]	53848	1		T95	2		T96	1		T5	1833
valid_sources[0x28]	53291	1		T96	4		T5	1921		T39	34
valid_sources[0x29]	53283	1		T95	4		T43	1		T96	4
valid_sources[0x2a]	51717	1		T29	1		T95	6		T96	3
valid_sources[0x2b]	52574	1		T95	2		T43	1		T96	4
valid_sources[0x2c]	51791	1		T95	1		T96	3		T5	1904
valid_sources[0x2d]	52614	1		T95	1		T5	1906		T39	41
valid_sources[0x2e]	52272	1		T30	1		T95	4		T96	1
valid_sources[0x2f]	53398	1		T33	3		T95	1		T96	3
valid_sources[0x30]	52635	1		T95	2		T96	4		T5	1913
valid_sources[0x31]	53175	1		T95	5		T96	2		T5	1915
valid_sources[0x32]	52787	1		T95	3		T96	6		T5	1895
valid_sources[0x33]	52543	1		T96	2		T5	1909		T39	33
valid_sources[0x34]	52396	1		T95	2		T5	1966		T39	43
valid_sources[0x35]	53323	1		T95	2		T96	1		T5	1871
valid_sources[0x36]	517427	1		T95	3		T96	1		T5	1924
valid_sources[0x37]	52445	1		T33	7		T95	1		T43	2
valid_sources[0x38]	53289	1		T95	7		T5	1731		T39	35
valid_sources[0x39]	52168	1		T28	2		T95	1		T96	3
valid_sources[0x3a]	53331	1		T95	2		T5	1891		T37	1
valid_sources[0x3b]	53887	1		T34	1		T95	5		T96	6
valid_sources[0x3c]	52835	1		T2	2		T95	1		T96	1
valid_sources[0x3d]	118680	1		T95	4		T96	1		T99	1
valid_sources[0x3e]	52358	1		T1	2		T42	6		T95	2
valid_sources[0x3f]	52569	1		T96	1		T5	1981		T39	32
valid_sources[0x40]	52233	1		T95	5		T96	2		T5	1904
valid_sources[0x41]	51434	1		T95	5		T4	19		T5	1915
valid_sources[0x42]	53847	1		T95	1		T96	1		T5	1902
valid_sources[0x43]	52721	1		T95	3		T96	1		T5	1950
valid_sources[0x44]	112950	1		T95	2		T96	2		T5	1824
valid_sources[0x45]	52769	1		T95	5		T5	1887		T39	43
valid_sources[0x46]	51459	1		T34	1		T95	7		T5	1928
valid_sources[0x47]	51687	1		T96	1		T5	1861		T39	54
valid_sources[0x48]	164567	1		T2	2		T29	1		T95	3
valid_sources[0x49]	51209	1		T95	1		T96	3		T93	1
valid_sources[0x4a]	52928	1		T95	5		T5	1896		T39	32
valid_sources[0x4b]	51311	1		T95	5		T96	1		T5	1900
valid_sources[0x4c]	53404	1		T95	3		T96	3		T5	1928
valid_sources[0x4d]	51694	1		T2	2		T95	8		T5	1838
valid_sources[0x4e]	53153	1		T1	1		T2	1		T28	1
valid_sources[0x4f]	679984	1		T95	5		T96	3		T5	1835
valid_sources[0x50]	50849	1		T1	1		T95	5		T96	3
valid_sources[0x51]	52545	1		T95	4		T96	5		T5	1899
valid_sources[0x52]	52393	1		T95	5		T96	2		T5	1905
valid_sources[0x53]	51597	1		T96	1		T5	1953		T39	52
valid_sources[0x54]	52248	1		T95	3		T96	1		T5	1782
valid_sources[0x55]	52612	1		T95	1		T96	2		T5	1736
valid_sources[0x56]	52092	1		T95	3		T5	1958		T37	1
valid_sources[0x57]	146044	1		T95	1		T96	1		T5	1898
valid_sources[0x58]	52278	1		T95	1		T96	5		T5	2015
valid_sources[0x59]	51089	1		T95	2		T96	4		T5	1806
valid_sources[0x5a]	52878	1		T95	6		T5	1694		T39	27
valid_sources[0x5b]	53676	1		T95	1		T96	5		T99	2
valid_sources[0x5c]	52399	1		T95	6		T96	2		T5	1925
valid_sources[0x5d]	127468	1		T95	1		T35	1		T96	3
valid_sources[0x5e]	270850	1		T95	1		T43	1		T96	1
valid_sources[0x5f]	52069	1		T95	4		T96	1		T5	1917
valid_sources[0x60]	53128	1		T95	6		T96	1		T5	1941
valid_sources[0x61]	150942	1		T95	1		T96	5		T5	1802
valid_sources[0x62]	53652	1		T95	4		T5	1869		T77	4
valid_sources[0x63]	53089	1		T95	6		T96	1		T5	1911
valid_sources[0x64]	51553	1		T95	1		T5	1903		T39	28
valid_sources[0x65]	53450	1		T31	2		T95	8		T96	1
valid_sources[0x66]	53784	1		T95	2		T96	1		T5	1803
valid_sources[0x67]	52888	1		T95	4		T96	6		T5	1904
valid_sources[0x68]	52772	1		T95	4		T5	1863		T39	43
valid_sources[0x69]	52416	1		T30	1		T95	1		T5	1868
valid_sources[0x6a]	51558	1		T95	3		T96	2		T5	1943
valid_sources[0x6b]	76953	1		T95	4		T35	1		T5	1937
valid_sources[0x6c]	52261	1		T1	1		T95	3		T96	2
valid_sources[0x6d]	53193	1		T95	2		T5	1859		T39	20
valid_sources[0x6e]	51290	1		T95	1		T96	3		T5	1817
valid_sources[0x6f]	52943	1		T95	6		T96	2		T5	1877
valid_sources[0x70]	53544	1		T28	4		T95	4		T96	2
valid_sources[0x71]	367813	1		T30	4		T95	5		T99	1
valid_sources[0x72]	53126	1		T95	4		T5	1817		T39	29
valid_sources[0x73]	53627	1		T95	3		T96	4		T5	1905
valid_sources[0x74]	52121	1		T95	3		T96	2		T5	1842
valid_sources[0x75]	52291	1		T95	5		T96	3		T5	1800
valid_sources[0x76]	52465	1		T95	2		T35	1		T96	2
valid_sources[0x77]	52888	1		T95	2		T35	3		T96	1
valid_sources[0x78]	52779	1		T95	2		T5	1951		T39	54
valid_sources[0x79]	53463	1		T29	3		T34	2		T95	3
valid_sources[0x7a]	52419	1		T95	4		T96	2		T5	2032
valid_sources[0x7b]	81760	1		T95	4		T96	1		T5	1947
valid_sources[0x7c]	52446	1		T95	6		T96	2		T5	1774
valid_sources[0x7d]	53034	1		T95	3		T35	1		T96	1
valid_sources[0x7e]	54379	1		T95	1		T96	5		T5	1961
valid_sources[0x7f]	52398	1		T33	1		T95	3		T96	4
valid_sources[0x80]	51783	1		T95	1		T96	4		T5	1944

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9053794

1

T1

5

T2

1

T3

1

values[0x0]

all_enables

biggest_size

149478

1

T1

4

T2

3

T3

4

values[0x1]

all_enables

biggest_size

138934

1

T1

3

T28

1

T29

2