Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	9003366	1		T1	5		T2	7		T3	5
full_word	9343152	1		T1	12		T2	4		T3	5

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	18346248	1		T1	17		T2	11		T3	10
auto[TlIntgErrCmd]	108	1		T114	6		T220	3		T221	10
auto[TlIntgErrData]	81	1		T114	3		T220	5		T221	3
auto[TlIntgErrBoth]	81	1		T114	1		T220	2		T221	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	17960807	1		T1	9		T2	4		T3	2
auto[1]	385711	1		T1	8		T2	7		T3	8

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8906695	1		T1	4		T2	3		T3	1
auto[TlIntgErrNone]	partial	auto[1]	96422	1		T1	1		T2	4		T3	4
auto[TlIntgErrNone]	full_word	auto[0]	9053977	1		T1	5		T2	1		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	289154	1		T1	7		T2	3		T3	4
auto[TlIntgErrCmd]	partial	auto[0]	49	1		T114	3		T221	6		T229	3
auto[TlIntgErrCmd]	partial	auto[1]	50	1		T114	1		T220	2		T221	4
auto[TlIntgErrCmd]	full_word	auto[0]	5	1		T114	2		T220	1		T233	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T291	1		T293	1		T292	1
auto[TlIntgErrData]	partial	auto[0]	35	1		T114	1		T220	3		T221	1
auto[TlIntgErrData]	partial	auto[1]	39	1		T114	1		T220	2		T221	2
auto[TlIntgErrData]	full_word	auto[0]	4	1		T114	1		T291	1		T290	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T290	1		T294	1		T295	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1		T221	3		T229	4		T296	2
auto[TlIntgErrBoth]	partial	auto[1]	36	1		T114	1		T220	2		T221	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T293	1		T294	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T221	1		T235	1		T289	1