Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.39	97.53	79.85	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	241576707	10513	0	0
ep_in_enable_rd_A	241576707	1882	0	0
ep_out_enable_rd_A	241576707	1736	0	0
in_iso_rd_A	241576707	2055	0	0
intr_enable_rd_A	241576707	2632	0	0
out_iso_rd_A	241576707	1672	0	0
phy_config_rd_A	241576707	1151	0	0
phy_pins_drive_rd_A	241576707	1504	0	0
rxenable_setup_rd_A	241576707	1838	0	0
set_nak_out_rd_A	241576707	1496	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241576707	10513	0	0
T112	4168	326	0	0
T113	4261	813	0	0
T114	28039	3	0	0
T216	5146	4	0	0
T220	14413	2	0	0
T221	41864	6	0	0
T222	3013	334	0	0
T229	28243	1	0	0
T232	7363	15	0	0
T233	25415	1	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241576707	1882	0	0
T114	28039	245	0	0
T216	5146	25	0	0
T221	41864	370	0	0
T231	10579	8	0	0
T234	9156	42	0	0
T248	3859	20	0	0
T262	18849	75	0	0
T265	5617	75	0	0
T266	38615	253	0	0
T267	14301	70	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241576707	1736	0	0
T114	28039	92	0	0
T216	5146	2	0	0
T221	41864	508	0	0
T231	10579	45	0	0
T234	9156	37	0	0
T248	3859	28	0	0
T262	18849	23	0	0
T265	5617	77	0	0
T266	38615	196	0	0
T267	14301	57	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241576707	2055	0	0
T114	28039	256	0	0
T216	5146	4	0	0
T221	41864	671	0	0
T231	10579	32	0	0
T234	9156	38	0	0
T248	3859	19	0	0
T262	18849	51	0	0
T265	5617	65	0	0
T266	38615	127	0	0
T267	14301	39	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241576707	2632	0	0
T114	28039	295	0	0
T119	5863	11	0	0
T216	5146	66	0	0
T221	41864	567	0	0
T231	10579	86	0	0
T234	9156	66	0	0
T248	3859	14	0	0
T262	18849	67	0	0
T265	5617	65	0	0
T266	38615	397	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241576707	1672	0	0
T114	28039	169	0	0
T216	5146	11	0	0
T221	41864	451	0	0
T231	10579	19	0	0
T234	9156	63	0	0
T248	3859	15	0	0
T262	18849	22	0	0
T265	5617	43	0	0
T266	38615	208	0	0
T267	14301	72	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241576707	1151	0	0
T114	28039	69	0	0
T216	5146	29	0	0
T221	41864	264	0	0
T231	10579	21	0	0
T234	9156	26	0	0
T248	3859	9	0	0
T262	18849	28	0	0
T265	5617	6	0	0
T266	38615	153	0	0
T267	14301	41	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241576707	1504	0	0
T114	28039	127	0	0
T216	5146	38	0	0
T221	41864	373	0	0
T231	10579	33	0	0
T234	9156	21	0	0
T248	3859	67	0	0
T262	18849	36	0	0
T265	5617	4	0	0
T266	38615	103	0	0
T267	14301	60	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241576707	1838	0	0
T114	28039	143	0	0
T216	5146	18	0	0
T221	41864	534	0	0
T231	10579	3	0	0
T248	3859	23	0	0
T262	18849	35	0	0
T265	5617	59	0	0
T266	38615	208	0	0
T267	14301	88	0	0
T268	61313	321	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241576707	1496	0	0
T114	28039	127	0	0
T221	41864	326	0	0
T231	10579	2	0	0
T234	9156	11	0	0
T248	3859	3	0	0
T262	18849	28	0	0
T265	5617	9	0	0
T266	38615	259	0	0
T267	14301	32	0	0
T269	3169	16	0	0